SLAS704G October   2012  – August 2018 MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics – Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics, Current Consumption per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.12.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.12.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Wake-up Characteristics
        1. Table 5-9   Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.12.4.1    Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.12.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.12.5.1    Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.12.5.2    Typical Characteristics, Pin-Oscillator Frequency
      6. 5.12.6  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode)
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode)
        5. Table 5-20 eUSCI (SPI Slave Mode)
        6. Table 5-21 eUSCI (I2C Mode)
      8. 5.12.8  ADC
        1. Table 5-22 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-23 12-Bit ADC, Timing Parameters
        3. Table 5-24 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 5-25 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 5-26 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 5-27 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 5-28 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 5-29 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 5-30 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 5-31 12-Bit ADC, External Reference
      9. 5.12.9  Reference
        1. Table 5-32 REF, Built-In Reference
      10. 5.12.10 Comparator
        1. Table 5-33 Comparator_E
      11. 5.12.11 FRAM
        1. Table 5-34 FRAM
    13. 5.13 Emulation and Debug
      1. Table 5-35 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
        1. 6.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM
    9. 6.9  Memory Protection Unit Including IP Encapsulation
    10. 6.10 Peripherals
      1. 6.10.1  Digital I/O
      2. 6.10.2  Oscillator and Clock System (CS)
      3. 6.10.3  Power-Management Module (PMM)
      4. 6.10.4  Hardware Multiplier (MPY)
      5. 6.10.5  Real-Time Clock (RTC_B) (Only MSP430FR596x and MSP430FR594x)
      6. 6.10.6  Watchdog Timer (WDT_A)
      7. 6.10.7  System Module (SYS)
      8. 6.10.8  DMA Controller
      9. 6.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.10.10 TA0, TA1
      11. 6.10.11 TA2, TA3
      12. 6.10.12 TB0
      13. 6.10.13 ADC12_B
      14. 6.10.14 Comparator_E
      15. 6.10.15 CRC16
      16. 6.10.16 AES256 Accelerator
      17. 6.10.17 True Random Seed
      18. 6.10.18 Shared Reference (REF)
      19. 6.10.19 Embedded Emulation
        1. 6.10.19.1 Embedded Emulation Module (EEM)
        2. 6.10.19.2 EnergyTrace++ Technology
      20. 6.10.20 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Capacitive Touch Functionality Ports P1, P2, P3, P4, and PJ
      2. 6.11.2  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P2 (P2.7) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      10. 6.11.10 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      11. 6.11.11 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      12. 6.11.12 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      13. 6.11.13 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
      14. 6.11.14 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      15. 6.11.15 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptor (TLV)
    13. 6.13 Identification
      1. 6.13.1 Revision Identification
      2. 6.13.2 Device Identification
      3. 6.13.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Interrupt Vector Table and Signatures

The interrupt vectors, the power-up start address and signatures are in the address range 0FFFFh to 0FF80h. Figure 6-1 summarizes the content of this address range.

MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 Interrupts_Signatures_Passwords.gifFigure 6-1 Interrupt Vectors, Signatures and Passwords

The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains a 16-bit address that points to the start address of the application program.

The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6-4 lists the device specific interrupt vector locations.

The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if enabled by the corresponding signature).

The signatures are located at 0FF80h extending to higher addresses. Signatures are evaluated during device start-up. Table 6-5 lists the device specific signature locations.

A JTAG password can be programmed starting from address 0FF88h and extending to higher addresses. The password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for the password. The length of the JTAG password depends on the JTAG signature.

See the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.

Table 6-4 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
System Reset
Power up, Brownout, Supply Supervisor
External Reset RST
Watchdog Time-out (Watchdog mode)
WDT, FRCTL MPU, CS, PMM Password Violation
FRAM uncorrectable bit error detection
MPU segment violation
FRAM access time error
Software POR, BOR		  
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG
ACCTEIFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV)(1)(2) 		Reset 0FFFEh highest
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM bit error detection
MPU segment violation		   
VMAIFG
JMBNIFG, JMBOUTIFG
CBDIFG, UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG
(SYSSNIV)(1)(3) 		(Non)maskable 0FFFCh
User NMI
External NMI
Oscillator Fault		 NMIIFG, OFIFG
(SYSUNIV)(1)(3) 		(Non)maskable 0FFFAh
Comparator_E CEIFG, CEIIFG
(CEIV)(1) 		Maskable 0FFF8h
TB0 TB0CCR0.CCIFG Maskable 0FFF6h
TB0 TB0CCR1.CCIFG ... TB0CCR6.CCIFG,
TB0CTL.TBIFG
(TB0IV)(1) 		Maskable 0FFF4h
Watchdog Timer (Interval Timer Mode) WDTIFG Maskable 0FFF2h
eUSCI_A0 Receive or Transmit UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode)
(UCA0IV)(1) 		Maskable 0FFF0h
eUSCI_B0 Receive or Transmit UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)(1) 		Maskable 0FFEEh
ADC12_B ADC12IFG0 to ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG, ADC12RDYIFG, ADC21OVIFG, ADC12TOVIFG
(ADC12IV)(1) 		Maskable 0FFECh
TA0 TA0CCR0.CCIFG Maskable 0FFEAh
TA0 TA0CCR1.CCIFG, TA0CCR2.CCIFG,
TA0CTL.TAIFG
(TA0IV)(1) 		Maskable 0FFE8h
eUSCI_A1 Receive or Transmit UCA1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode)
(UCA1IV)(1) 		Maskable 0FFE6h
DMA DMA0CTL.DMAIFG, DMA1CTL.DMAIFG, DMA2CTL.DMAIFG
(DMAIV)(1) 		Maskable 0FFE4h
TA1 TA1CCR0.CCIFG Maskable 0FFE2h
TA1 TA1CCR1.CCIFG, TA1CCR2.CCIFG,
TA1CTL.TAIFG
(TA1IV)(1) 		Maskable 0FFE0h
I/O Port P1 P1IFG.0 to P1IFG.7
(P1IV)(1) 		Maskable 0FFDEh
TA2 TA2CCR0.CCIFG Maskable 0FFDCh
TA2 TA2CCR1.CCIFG
TA2CTL.TAIFG
(TA2IV)(1) 		Maskable 0FFDAh
I/O Port P2 P2IFG.0 to P2IFG.7
(P2IV)(1) 		Maskable 0FFD8h
TA3 TA3CCR0.CCIFG Maskable 0FFD6h
TA3 TA3CCR1.CCIFG
TA3CTL.TAIFG
(TA3IV)(1) 		Maskable 0FFD4h
I/O Port P3 P3IFG.0 to P3IFG.7
(P3IV)(1) 		Maskable 0FFD2h
I/O Port P4 P4IFG.0 to P4IFG.2
(P4IV)(1) 		Maskable 0FFD0h
RTC_B RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG
(RTCIV)(1) 		Maskable 0FFCEh
AES AESRDYIFG Maskable 0FFCCh lowest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space
(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.

Table 6-5 Signatures

SIGNATURE WORD ADDRESS
IP Encapsulation Signature 2 0FF8Ah
IP Encapsulation Signature 1(1) 0FF88h
BSL Signature 2 0FF86h
BSL Signature 1 0FF84h
JTAG Signature 2 0FF82h
JTAG Signature 1 0FF80h
(1) Must not contain 0AAAAh if used as JTAG password and IP encapsulation functionality is not desired.