SLASE66C April   2015  – August 2018 MSP430FR5870 , MSP430FR5872 , MSP430FR58721 , MSP430FR5922 , MSP430FR59221 , MSP430FR5970 , MSP430FR5972 , MSP430FR59721

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics - Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics, Current Consumption per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.12.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.12.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Wake-up Characteristics
        1. Table 5-9   Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.12.4.1    Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.12.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.12.5.1    Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.12.5.2    Typical Characteristics, Pin-Oscillator Frequency
      6. 5.12.6  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode)
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode)
        5. Table 5-20 eUSCI (SPI Slave Mode)
        6. Table 5-21 eUSCI (I2C Mode)
      8. 5.12.8  ADC12
        1. Table 5-22 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-23 12-Bit ADC, Timing Parameters
        3. Table 5-24 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 5-25 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 5-26 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 5-27 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 5-28 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 5-29 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 5-30 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 5-31 12-Bit ADC, External Reference
      9. 5.12.9  REF Module
        1. Table 5-32 REF, Built-In Reference
      10. 5.12.10 Comparator
        1. Table 5-33 Comparator_E
      11. 5.12.11 FRAM Controller
        1. Table 5-34 FRAM
      12. 5.12.12 Emulation and Debug
        1. Table 5-35 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
      2. 6.3.2 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  FRAM
    8. 6.8  RAM
    9. 6.9  Tiny RAM
    10. 6.10 Memory Protection Unit (MPU) Including IP Encapsulation
    11. 6.11 Peripherals
      1. 6.11.1  Digital I/O
      2. 6.11.2  Oscillator and Clock System (CS)
      3. 6.11.3  Power-Management Module (PMM)
      4. 6.11.4  Hardware Multiplier
      5. 6.11.5  Real-Time Clock (RTC_C)
      6. 6.11.6  Watchdog Timer (WDT_A)
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  DMA Controller
      9. 6.11.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.11.10 Timer_A TA0, Timer_A TA1
      11. 6.11.11 Timer_A TA2
      12. 6.11.12 Timer_A TA3
      13. 6.11.13 Timer_B TB0
      14. 6.11.14 ADC12_B
      15. 6.11.15 Comparator_E
      16. 6.11.16 CRC16
      17. 6.11.17 CRC32
      18. 6.11.18 AES256 Accelerator
      19. 6.11.19 True Random Seed
      20. 6.11.20 Shared Reference (REF_A)
      21. 6.11.21 Embedded Emulation
        1. 6.11.21.1 Embedded Emulation Module (EEM)
        2. 6.11.21.2 EnergyTrace++ Technology
      22. 6.11.22 Input/Output Diagrams
        1. 6.11.22.1  Digital I/O Functionality Port P1 to P7 and P9
        2. 6.11.22.2  Capacitive Touch Functionality on Port P1 to P7, P9, and PJ
        3. 6.11.22.3  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
        4. 6.11.22.4  Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
        5. 6.11.22.5  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
        6. 6.11.22.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
        7. 6.11.22.7  Port P4 (P4.2 to P4.7) Input/Output With Schmitt Trigger
        8. 6.11.22.8  Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger
        9. 6.11.22.9  Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
        10. 6.11.22.10 Port P7 (P7.0 to P7.4) Input/Output With Schmitt Trigger
        11. 6.11.22.11 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
        12. 6.11.22.12 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
        13. 6.11.22.13 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
        14. 6.11.22.14 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Memory
      1. 6.13.1 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.3 Signal Descriptions

Table 4-2 describes the signals.

Table 4-2 Signal Descriptions

FUNCTION SIGNAL NAME FR597x(1), FR587x(1) FR592x(1) SIGNAL TYPE DESCRIPTION
PM, RGC PM, RGC DGG
PIN NO. PIN NO. PIN NO.
ADC A0 44 44 47 I Analog input A0
A1 43 43 46 I Analog input A1
A2 42 42 45 I Analog input A2
A3 41 41 44 I Analog input A3
A12 45 45 48 I Analog input A12
A13 46 46 49 I Analog input A13
A14 47 47 50 I Analog input A14
A15 48 48 51 I Analog input A15
VREF+ 43 43 46 O Output of positive reference voltage
VREF- 44 44 47 O Output of negative reference voltage
VeREF+ 43 43 46 I Input for an external positive reference voltage to the ADC
VeREF- 44 44 47 I Input for an external negative reference voltage to the ADC
BSL (I2C) BSL_CLK 5 5 10 I BSL Clock (I2C BSL)
BSL_DAT 4 4 9 I BSL Data (I2C BSL)
BSL (UART) BSL_RX 32 32 35 I BSL Receive (UART BSL)
BSL_TX 33 33 36 O BSL Transmit (UART BSL)
Clock ACLK 23
35		 23
35		 26
38		 O ACLK output
HFXIN 55 I Input terminal of crystal oscillator XT2
HFXOUT 54 O Output terminal for crystal oscillator XT2
LFXIN 51 51 54 I Input terminal for crystal oscillator XT1
LFXOUT 52 52 55 O Output terminal of crystal oscillator XT1
MCLK 22 22 25 O MCLK output
RTCCLK 31
44		 31
44		 34
47		 O RTC clock output for calibration
SMCLK 21
38		 21
38		 24
41		 O SMCLK output
Comparator C0 44 44 47 I Comparator input C0
C1 43 43 46 I Comparator input C1
C2 42 42 45 I Comparator input C2
C3 41 41 44 I Comparator input C3
C12 45 45 48 I Comparator input C12
C13 46 46 49 I Comparator input C13
C14 47 47 50 I Comparator input C14
C15 48 48 51 I Comparator input C15
COUT 9
24
42
43		 9
24
42
43		 14
27
45
46		 O Comparator output
DMA DMAE0 32
44		 32
44		 32
44		 I DMA external trigger input
DNC DNC 6 6 22 – Do Not Connect (DNC). TI strongly recommends leaving this pin not connected.
Debug SBWTCK 19 19 23 I Spy-Bi-Wire input clock
SBWTDIO 20 20 27 I/O Spy-Bi-Wire data input/output
SRCPUOFF 24 24 26 O Low-power debug: CPU status register CPUOFF
SROSCOFF 23 23 25 O Low-power debug: CPU status register OSCOFF
SRSCG0 22 22 24 O Low-power debug: CPU status register SCG0
SRSCG1 21 21 27 O Low-power debug: CPU status register SCG1
TCK 24 24 25 I Test clock
TCLK 22 22 25 I Test clock input
TDI 22 22 24 I Test data input
TDO 21 21 22 O Test data output port
TEST 19 19 26 I Test mode pin - select digital I/O on JTAG pins
TMS 23 23 23 I Test mode select
GPIO P1.0 44 44 47 I/O General-purpose digital I/O
P1.1 43 43 46 I/O General-purpose digital I/O
P1.2 42 42 45 I/O General-purpose digital I/O
P1.3 41 41 44 I/O General-purpose digital I/O
P1.4 2 2 7 I/O General-purpose digital I/O
P1.5 3 3 8 I/O General-purpose digital I/O
P1.6 4 4 9 I/O General-purpose digital I/O
P1.7 5 5 10 I/O General-purpose digital I/O
P2.0 33 33 36 I/O General-purpose digital I/O
P2.1 32 32 35 I/O General-purpose digital I/O
P2.2 31 31 34 I/O General-purpose digital I/O
P2.3 30 30 33 I/O General-purpose digital I/O
P3.0 14 14 19 I/O General-purpose digital I/O
P3.1 15 15 20 I/O General-purpose digital I/O
P3.2 16 16 21 I/O General-purpose digital I/O
P3.3 25 25 28 I/O General-purpose digital I/O
P3.4 26 26 29 I/O General-purpose digital I/O
P3.5 27 27 30 I/O General-purpose digital I/O
P3.6 28 28 31 I/O General-purpose digital I/O
P3.7 29 29 32 I/O General-purpose digital I/O
P4.2 64 64 I/O General-purpose digital I/O
P4.3 1 1 I/O General-purpose digital I/O
P4.4 58 58 1 I/O General-purpose digital I/O
P4.5 59 59 2 I/O General-purpose digital I/O
P4.6 60 60 3 I/O General-purpose digital I/O
P4.7 61 61 4 I/O General-purpose digital I/O
P5.4 54 I/O General-purpose digital I/O
P5.5 55 I/O General-purpose digital I/O
P5.6 56 I/O General-purpose digital I/O
P5.7 57 57 I/O General-purpose digital I/O
GPIO P6.0 7 7 12 I/O General-purpose digital I/O
P6.1 8 8 13 I/O General-purpose digital I/O
P6.2 9 9 14 I/O General-purpose digital I/O
P6.3 10 10 15 I/O General-purpose digital I/O
P6.4 11 11 16 I/O General-purpose digital I/O
P6.5 12 12 17 I/O General-purpose digital I/O
P6.6 13 13 18 I/O General-purpose digital I/O
P7.0 34 34 37 I/O General-purpose digital I/O
P7.1 35 35 38 I/O General-purpose digital I/O
P7.2 36 36 39 I/O General-purpose digital I/O
P7.3 37 37 40 I/O General-purpose digital I/O
P7.4 38 38 41 I/O General-purpose digital I/O
P9.4 45 45 48 I/O General-purpose digital I/O
P9.5 46 46 49 I/O General-purpose digital I/O
P9.6 47 47 50 I/O General-purpose digital I/O
P9.7 48 48 51 I/O General-purpose digital I/O
PJ.0 21 21 24 I/O General-purpose digital I/O
PJ.1 22 22 25 I/O General-purpose digital I/O
PJ.2 23 23 26 I/O General-purpose digital I/O
PJ.3 24 24 27 I/O General-purpose digital I/O
PJ.4 51 51 54 I/O General-purpose digital I/O
PJ.5 52 52 55 I/O General-purpose digital I/O
PJ.6 55 55 I/O General-purpose digital I/O
PJ.7 54 54 I/O General-purpose digital I/O
I2C UCB0SCL 5 5 10 I/O USCI_B0: I2C clock (I2C mode)
UCB0SDA 4 4 9 I/O USCI_B0: I2C data (I2C mode)
UCB1SCL 16
61		 16
61		 21
4		 I/O USCI_B1: I2C clock (I2C mode)
UCB1SDA 15
60		 15
60		 20
3		 I/O USCI_B1: I2C data (I2C mode)
Power AVCC1 49 49 52 P Analog power supply
AVSS1 50 50 53 P Analog ground supply
AVSS2 53 53 56 P Analog ground supply
AVSS3 56 P Analog ground supply
DVCC1 18 18 P Digital power supply
DVCC2 40 40 43 P Digital power supply
DVCC3 63 63 6 P Digital power supply
DVSS1 17 17 P Digital ground supply
DVSS2 39 39 42 P Digital ground supply
DVSS3 62 62 5 P Digital ground supply
SPI UCA0CLK 3
31		 3
31		 8
34		 I/O USCI_A0: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
UCA0SIMO 33
64		 33
64		 36 I/O USCI_A0: Slave in, master out (SPI mode)
UCA0SOMI 1
32		 1
32		 35 I/O USCI_A0: Slave out, master in (SPI mode)
UCA0STE 2
30		 2
30		 7
33		 I/O USCI_A0: Slave transmit enable (SPI mode)
UCA1CLK 28 28
56		 31 I/O USCI_A1: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
UCA1SIMO 26 26
54		 29 I/O USCI_A1: Slave in, master out (SPI mode)
UCA1SOMI 27 27
55		 30 I/O USCI_A1: Slave out, master in (SPI mode)
UCA1STE 29
57		 29
57		 32 I/O

USCI_A1: Slave transmit enable (SPI mode)
UCB0CLK 2 2 7 I/O USCI_B0: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
UCB0SIMO 4 4 9 I/O USCI_B0: Slave in, master out (SPI mode)
UCB0SOMI 5 5 10 I/O USCI_B0: Slave out, master in (SPI mode)
UCB0STE 3 3 8 I/O USCI_B0: Slave transmit enable (SPI mode)
UCB1CLK 14
59
64		 14
59
64		 19
2		 I/O USCI_B1: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
UCB1SIMO 15
60		 15
60		 3
20		 I/O USCI_B1: Slave in, master out (SPI mode)
UCB1SOMI 16
61		 16
61		 21
4		 I/O USCI_B1: Slave out, master in (SPI mode)
UCB1STE 1
58		 1
58		 1 I/O USCI_B1: Slave transmit enable (SPI mode)
System NMI 20 20 23 I Nonmaskable interrupt input
RST 20 20 23 I Reset input active low
Timer_A TA0.0 3
35		 3
35		 8
38		 I/O Timer_A TA0 CCR0 capture: CCI0A input, compare: Out0 output
TA0.1 4
36
44		 4
36
44		 9
39
47		 I/O Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output
TA0.2 5
37
43		 5
37
43		 10
40
46		 I/O Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output
TA0CLK 34
42		 34
42		 37
45		 I Timer_A TA0 clock signal TA0CLK input
TA1.0 2
59		 2
59		 7
2		 I/O Timer_A TA1 CCR0 capture: CCI0A input, compare: Out0 output
TA1.1 25
42
60		 25
42
60		 28
45
3		 I/O Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
TA1.2 41
61		 41
61		 44
4		 I/O Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output
TA1CLK 43
58		 43
58		 46
1		 I Timer_A TA1 clock signal TA1CLK input
TA3.2 14 14 19 I/O Timer_A TA3 CCR2 capture: CCI2B input, compare: Out2 output
TA3.3 15 15 20 I/O Timer_A TA3 CCR3 capture: CCI3B input, compare: Out3 output
TA3.4 16 16 21 I/O Timer_A TA3 CCR4 capture: CCI4B input, compare: Out4 output
Timer_B TB0.0 11
26		 11
26		 16
29		 I/O Timer_B TB0 CCR0 capture: CCI0B input, compare: Out0 output
TB0.1 12
27		 12
27		 17
30		 I/O Timer_B TB0 CCR1 capture: CCI1A input, compare: Out1 output
TB0.2 13
28		 13
28		 18
31		 I/O Timer_B TB0 CCR2 capture: CCI2A input, compare: Out2 output
TB0.3 29 29 32 I/O Timer_B TB0 CCR3 capture: CCI3B input, compare: Out3 output
TB0.4 31 31 34 I/O Timer_B TB0 CCR4 capture: CCI4B input, compare: Out4 output
TB0.5 32 32 35 I/O Timer_B TB0 CCR5 capture: CCI5B input, compare: Out5 output
TB0.6 33 33 36 I/O Timer_B TB0 CCR6 capture: CCI6B input, compare: Out6 output
TB0CLK 25
33
57		 25
33
57		 28
36		 I Timer_B TB0 clock signal TB0CLK input
TB0OUTH 21
30		 21
30		 24
33		 I Switch all PWM outputs high impedance input - Timer_B TB0
UART UCA0RXD 1
32		 1
32		 35 I USCI_A0: Receive data (UART mode)
UCA0TXD 33
64		 33
64		 36 O USCI_A0: Transmit data (UART mode)
UCA1RXD 27 27 30 I USCI_A1: Receive data (UART mode)
UCA1TXD 26 26 29 O USCI_A1: Transmit data (UART mode)
Thermal Pad RGC package only. VQFN package exposed thermal pad. TI recommends connection to VSS.