SLASEC9 April   2017 MSP430FR5989-EP

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Signal Descriptions
    3. 3.3 Pin Multiplexing
    4. 3.4 Connection of Unused Pins
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Typical Characteristics, Active Mode Supply Currents
    6. 4.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    10. 4.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 4.11 Typical Characteristics, Current Consumption per Module
    12. 4.12 Thermal Resistance Characteristics
    13. 4.13 Timing and Switching Characteristics
      1. 4.13.1 Power Supply Sequencing
      2. 4.13.2 Reset Timing
      3. 4.13.3 Clock Specifications
      4. 4.13.4 Wake-up Characteristics
        1. 4.13.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 4.13.5 Peripherals
        1. 4.13.5.1 Digital I/Os
          1. 4.13.5.1.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
          2. 4.13.5.1.2 Typical Characteristics, Pin-Oscillator Frequency
        2. 4.13.5.2 Timer_A and Timer_B
        3. 4.13.5.3 eUSCI
        4. 4.13.5.4 LCD Controller
        5. 4.13.5.5 ADC
        6. 4.13.5.6 Reference
        7. 4.13.5.7 Comparator
        8. 4.13.5.8 Scan Interface
        9. 4.13.5.9 FRAM Controller
      6. 4.13.6 Emulation and Debug
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  CPU
    3. 5.3  Operating Modes
      1. 5.3.1 Peripherals in Low-Power Modes
        1. 5.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 5.4  Interrupt Vector Table and Signatures
    5. 5.5  Bootloader (BSL)
    6. 5.6  JTAG Operation
      1. 5.6.1 JTAG Standard Interface
      2. 5.6.2 Spy-Bi-Wire Interface
    7. 5.7  FRAM
    8. 5.8  RAM
    9. 5.9  Tiny RAM
    10. 5.10 Memory Protection Unit Including IP Encapsulation
    11. 5.11 Peripherals
      1. 5.11.1  Digital I/O
      2. 5.11.2  Oscillator and Clock System (CS)
      3. 5.11.3  Power-Management Module (PMM)
      4. 5.11.4  Hardware Multiplier (MPY)
      5. 5.11.5  Real-Time Clock (RTC_C)
      6. 5.11.6  Watchdog Timer (WDT_A)
      7. 5.11.7  System Module (SYS)
      8. 5.11.8  DMA Controller
      9. 5.11.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 5.11.10 Extended Scan Interface (ESI)
      11. 5.11.11 Timer_A TA0, Timer_A TA1
      12. 5.11.12 Timer_A TA2
      13. 5.11.13 Timer_A TA3
      14. 5.11.14 Timer_B TB0
      15. 5.11.15 ADC12_B
      16. 5.11.16 Comparator_E
      17. 5.11.17 CRC16
      18. 5.11.18 CRC32
      19. 5.11.19 AES256 Accelerator
      20. 5.11.20 True Random Seed
      21. 5.11.21 Shared Reference (REF_A)
      22. 5.11.22 LCD_C
      23. 5.11.23 Embedded Emulation
        1. 5.11.23.1 Embedded Emulation Module (EEM)
        2. 5.11.23.2 EnergyTrace++™ Technology
      24. 5.11.24 Input/Output Diagrams
        1. 5.11.24.1  Digital I/O Functionality - Ports P1 to P10
        2. 5.11.24.2  Capacitive Touch Functionality Ports P1 to P10 and PJ
        3. 5.11.24.3  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
        4. 5.11.24.4  Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
        5. 5.11.24.5  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
        6. 5.11.24.6  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
        7. 5.11.24.7  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
        8. 5.11.24.8  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
        9. 5.11.24.9  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
        10. 5.11.24.10 Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
        11. 5.11.24.11 Port P6 (P6.7) Input/Output With Schmitt Trigger
        12. 5.11.24.12 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger
        13. 5.11.24.13 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
        14. 5.11.24.14 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
        15. 5.11.24.15 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
        16. 5.11.24.16 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
        17. 5.11.24.17 Port P10 (P10.0 to P10.2) Input/Output With Schmitt Trigger
        18. 5.11.24.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
        19. 5.11.24.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
        20. 5.11.24.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptors (TLV)
    13. 5.13 Memory
      1. 5.13.1 Peripheral File Map
    14. 5.14 Identification
      1. 5.14.1 Revision Identification
      2. 5.14.2 Device Identification
      3. 5.14.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Device Connection and Layout Fundamentals
      1. 6.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.1.2 External Oscillator
      3. 6.1.3 JTAG
      4. 6.1.4 Reset
      5. 6.1.5 Unused Pins
      6. 6.1.6 General Layout Recommendations
      7. 6.1.7 Do's and Don'ts
    2. 6.2 Peripheral- and Interface-Specific Design Information
      1. 6.2.1 ADC12_B Peripheral
        1. 6.2.1.1 Partial Schematic
        2. 6.2.1.2 Design Requirements
        3. 6.2.1.3 Detailed Design Procedure
        4. 6.2.1.4 Layout Guidelines
      2. 6.2.2 LCD_C Peripheral
        1. 6.2.2.1 Partial Schematic
        2. 6.2.2.2 Design Requirements
        3. 6.2.2.3 Detailed Design Procedure
        4. 6.2.2.4 Layout Guidelines
  7. 7Device and Documentation Support
    1. 7.1 Device and Development Tool Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Revision History

DATE REVISION NOTES
April 2017 * Initial release.