SLASEC9 April   2017 MSP430FR5989-EP

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Signal Descriptions
    3. 3.3 Pin Multiplexing
    4. 3.4 Connection of Unused Pins
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 4.5  Typical Characteristics, Active Mode Supply Currents
    6. 4.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 4.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 4.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 4.9  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    10. 4.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 4.11 Typical Characteristics, Current Consumption per Module
    12. 4.12 Thermal Resistance Characteristics
    13. 4.13 Timing and Switching Characteristics
      1. 4.13.1 Power Supply Sequencing
      2. 4.13.2 Reset Timing
      3. 4.13.3 Clock Specifications
      4. 4.13.4 Wake-up Characteristics
        1. 4.13.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 4.13.5 Peripherals
        1. 4.13.5.1 Digital I/Os
          1. 4.13.5.1.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
          2. 4.13.5.1.2 Typical Characteristics, Pin-Oscillator Frequency
        2. 4.13.5.2 Timer_A and Timer_B
        3. 4.13.5.3 eUSCI
        4. 4.13.5.4 LCD Controller
        5. 4.13.5.5 ADC
        6. 4.13.5.6 Reference
        7. 4.13.5.7 Comparator
        8. 4.13.5.8 Scan Interface
        9. 4.13.5.9 FRAM Controller
      6. 4.13.6 Emulation and Debug
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  CPU
    3. 5.3  Operating Modes
      1. 5.3.1 Peripherals in Low-Power Modes
        1. 5.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 5.4  Interrupt Vector Table and Signatures
    5. 5.5  Bootloader (BSL)
    6. 5.6  JTAG Operation
      1. 5.6.1 JTAG Standard Interface
      2. 5.6.2 Spy-Bi-Wire Interface
    7. 5.7  FRAM
    8. 5.8  RAM
    9. 5.9  Tiny RAM
    10. 5.10 Memory Protection Unit Including IP Encapsulation
    11. 5.11 Peripherals
      1. 5.11.1  Digital I/O
      2. 5.11.2  Oscillator and Clock System (CS)
      3. 5.11.3  Power-Management Module (PMM)
      4. 5.11.4  Hardware Multiplier (MPY)
      5. 5.11.5  Real-Time Clock (RTC_C)
      6. 5.11.6  Watchdog Timer (WDT_A)
      7. 5.11.7  System Module (SYS)
      8. 5.11.8  DMA Controller
      9. 5.11.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 5.11.10 Extended Scan Interface (ESI)
      11. 5.11.11 Timer_A TA0, Timer_A TA1
      12. 5.11.12 Timer_A TA2
      13. 5.11.13 Timer_A TA3
      14. 5.11.14 Timer_B TB0
      15. 5.11.15 ADC12_B
      16. 5.11.16 Comparator_E
      17. 5.11.17 CRC16
      18. 5.11.18 CRC32
      19. 5.11.19 AES256 Accelerator
      20. 5.11.20 True Random Seed
      21. 5.11.21 Shared Reference (REF_A)
      22. 5.11.22 LCD_C
      23. 5.11.23 Embedded Emulation
        1. 5.11.23.1 Embedded Emulation Module (EEM)
        2. 5.11.23.2 EnergyTrace++™ Technology
      24. 5.11.24 Input/Output Diagrams
        1. 5.11.24.1  Digital I/O Functionality - Ports P1 to P10
        2. 5.11.24.2  Capacitive Touch Functionality Ports P1 to P10 and PJ
        3. 5.11.24.3  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
        4. 5.11.24.4  Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
        5. 5.11.24.5  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
        6. 5.11.24.6  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
        7. 5.11.24.7  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
        8. 5.11.24.8  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
        9. 5.11.24.9  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
        10. 5.11.24.10 Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
        11. 5.11.24.11 Port P6 (P6.7) Input/Output With Schmitt Trigger
        12. 5.11.24.12 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger
        13. 5.11.24.13 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
        14. 5.11.24.14 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
        15. 5.11.24.15 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
        16. 5.11.24.16 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
        17. 5.11.24.17 Port P10 (P10.0 to P10.2) Input/Output With Schmitt Trigger
        18. 5.11.24.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
        19. 5.11.24.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
        20. 5.11.24.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 5.12 Device Descriptors (TLV)
    13. 5.13 Memory
      1. 5.13.1 Peripheral File Map
    14. 5.14 Identification
      1. 5.14.1 Revision Identification
      2. 5.14.2 Device Identification
      3. 5.14.3 JTAG Identification
  6. 6Applications, Implementation, and Layout
    1. 6.1 Device Connection and Layout Fundamentals
      1. 6.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 6.1.2 External Oscillator
      3. 6.1.3 JTAG
      4. 6.1.4 Reset
      5. 6.1.5 Unused Pins
      6. 6.1.6 General Layout Recommendations
      7. 6.1.7 Do's and Don'ts
    2. 6.2 Peripheral- and Interface-Specific Design Information
      1. 6.2.1 ADC12_B Peripheral
        1. 6.2.1.1 Partial Schematic
        2. 6.2.1.2 Design Requirements
        3. 6.2.1.3 Detailed Design Procedure
        4. 6.2.1.4 Layout Guidelines
      2. 6.2.2 LCD_C Peripheral
        1. 6.2.2.1 Partial Schematic
        2. 6.2.2.2 Design Requirements
        3. 6.2.2.3 Detailed Design Procedure
        4. 6.2.2.4 Layout Guidelines
  7. 7Device and Documentation Support
    1. 7.1 Device and Development Tool Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Terminal Configuration and Functions

3.1 Pin Diagram

Figure 3-1 shows the pinout of the 64-pin RGC package.

MSP430FR5989-EP MSP430F588x_64QFP.gif

NOTE:

TI recommends connecting the RGC package pad to VSS.

NOTE:

On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX

NOTE:

On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 3-1 64-Pin RGC Package (Top View) – MSP430FR5989-EP

3.2 Signal Descriptions

Table 3-1 Signal Descriptions – MSP430FR5989-EP

TERMINAL DESCRIPTION
NAME RGC
NO.
P4.3/UCA0SOMI/ UCA0RXD/UCB1STE 1 General-purpose digital I/O

USCI_A0: Slave out, master in (SPI mode), Receive data (UART mode)

USCI_B1: Slave transmit enable (SPI mode)
P1.4/UCB0CLK/ UCA0STE/TA1.0 2 General-purpose digital I/O

USCI_B0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

USCI_A0: Slave transmit enable (SPI mode)

Timer_A TA1 CCR0 capture: CCI0A input, compare: Out0 output
P1.5/UCB0STE/ UCA0CLK/TA0.0 3 General-purpose digital I/O

USCI_B0: Slave transmit enable (SPI mode)

USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

Timer_A TA0 CCR0 capture: CCI0A input, compare: Out0 output

P1.6/UCB0SIMO/ UCB0SDA/TA0.1 4 General-purpose digital I/O

USCI_B0: Slave in, master out (SPI mode), I2C data (I2C mode)

BSL Data (I2C BSL)

Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output

P1.7/UCB0SOMI/ UCB0SCL/TA0.2 5 General-purpose digital I/O

USCI_B0: Slave out, master in (SPI mode), I2C clock (I2C mode)

BSL Clock (I2C BSL)

Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output

P2.4/TB0.3 6 General-purpose digital I/O

Timer_B TB0 CCR3 capture: CCI3A input, compare: Out3 output

P2.5/TB0.4 7 General-purpose digital I/O

Timer_B TB0 CCR4 capture: CCI4A input, compare: Out4 output

P2.6/TB0.5/ESIC1OUT 8 General-purpose digital I/O

Timer_B TB0 CCR5 capture: CCI5A input, compare: Out5 output

ESI Comparator 1 output
P2.7/TB0.6/ESIC2OUT 9 General-purpose digital I/O

Timer_B TB0 CCR6 capture: CCI6A input, compare: Out6 output

ESI Comparator 2 output
P5.0/TA1.1/MCLK 10 General-purpose digital I/O

Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output

MCLK output

P5.1/TA1.2 11 General-purpose digital I/O

Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output

P5.2/TA1.0/TA1CLK/ACLK 12 General-purpose digital I/O

Timer_A TA1 CCR0 capture: CCI0B input, compare: Out0 output

Timer_A TA1 clock signal TA0CLK input

ACLK output
P5.3/UCB1STE 13 General-purpose digital I/O

USCI_B1: Slave transmit enable (SPI mode)

P3.0/UCB1CLK 14 General-purpose digital I/O

USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

P3.1/UCB1SIMO/UCB1SDA 15 General-purpose digital I/O

USCI_B1: Slave in, master out (SPI mode)

USCI_B1: I2C data (I2C mode)

P3.2/UCB1SOMI/UCB1SCL 16 General-purpose digital I/O

USCI_B1: Slave out, master in (SPI mode)

USCI_B1: I2C clock (I2C mode)

DVSS1 17 Digital ground supply
DVCC1 18 Digital power supply
TEST/SBWTCK 19 Test mode pin - select digital I/O on JTAG pins

Spy-Bi-Wire input clock
RST/NMI/SBWTDIO 20 Reset input, active low

Nonmaskable interrupt input

Spy-Bi-Wire data input/output
PJ.0/TDO/TB0OUTH/ SMCLK/SRSCG1 21 General-purpose digital I/O

Test data output port

Switch all PWM outputs high impedance input - Timer_B TB0

SMCLK output

Low-power debug: CPU Status register SCG1
PJ.1/TDI/TCLK/MCLK/SRSCG0 22 General-purpose digital I/O

Test data input or test clock input

MCLK output

Low-power debug: CPU Status register SCG0
PJ.2/TMS/ACLK/SROSCOFF 23 General-purpose digital I/O

Test mode select

ACLK output

Low-power debug: CPU Status register OSCOFF
PJ.3/TCK/COUT/SRCPUOFF 24 General-purpose digital I/O

Test clock

Comparator output

Low-power debug: CPU Status register CPUOFF
P3.3/TA1.1/TB0CLK 25 General-purpose digital I/O

Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output

Timer_B TB0 clock signal TB0CLK input

P3.4/UCA1SIMO/UCA1TXD/TB0.0 26 General-purpose digital I/O

USCI_A1: Slave in, master out (SPI mode)

USCI_A1: Transmit data (UART mode)

Timer_B TB0 CCR0 capture: CCI0A input, compare: Out0 output

P3.5/UCA1SOMI/UCA1RXD/TB0.1 27 General-purpose digital I/O

USCI_A1: Slave out, master in (SPI mode)

USCI_A1: Receive data (UART mode)

Timer_B TB0 CCR1 capture: CCI1A input, compare: Out1 output

P3.6/UCA1CLK/TB0.2 28 General-purpose digital I/O

USCI_A1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

Timer_B TB0 CCR2 capture: CCI2A input, compare: Out2 output

P3.7/UCA1STE/TB0.3 29 General-purpose digital I/O

USCI_A1: Slave transmit enable (SPI mode)

Timer_B TB0 CCR3 capture: CCI3B input, compare: Out3 output

P2.3/UCA0STE/TB0OUTH 30 General-purpose digital I/O

USCI_A0: Slave transmit enable (SPI mode)

Switch all PWM outputs high impedance input - Timer_B TB0

P2.2/UCA0CLK/TB0.4/RTCCLK 31 General-purpose digital I/O

USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)

Timer_B TB0 CCR4 capture: CCI4B input, compare: Out4 output

RTC clock output for calibration

P2.1/UCA0SOMI/UCA0RXD/TB0.5/ DMAE0 32 General-purpose digital I/O

USCI_A0: Slave out, master in (SPI mode)

USCI_A0: Receive data (UART mode)

BSL receive (UART BSL)

Timer_B TB0 CCR5 capture: CCI5B input, compare: Out5 output

DMA external trigger input
P2.0/UCA0SIMO/UCA0TXD/TB0.6/ TB0CLK 33 General-purpose digital I/O

USCI_A0: Slave in, master out (SPI mode)

USCI_A0: Transmit data (UART mode)

BSL transmit (UART BSL)

Timer_B TB0 CCR6 capture: CCI6B input, compare: Out6 output

Timer_B TB0 clock signal TB0CLK input

DVSS2 34 Digital ground supply
DVCC2 35 Digital power supply
P1.3/ESITEST4/TA1.2/A3/C3 36 General-purpose digital I/O

ESI test signal 4

Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output

Analog input A3

Comparator input C3
P1.2/TA1.1/TA0CLK/COUT/A2/C2 37 General-purpose digital I/O

Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output

Timer_A TA0 clock signal TA0CLK input

Comparator output

Analog input A2

Comparator input C2
P1.1/TA0.2/TA1CLK/ COUT/A1/C1/VREF+/ VeREF+ 38 General-purpose digital I/O

Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output

Timer_A TA1 clock signal TA1CLK input

Comparator output

Analog input A1

Comparator input C1

Output of positive reference voltage

Input for an external positive reference voltage to the ADC
P1.0/TA0.1/DMAE0/ RTCCLK/A0/C0/ VREF-/VeREF- 39 General-purpose digital I/O

Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output

DMA external trigger input

RTC clock output for calibration

Analog input A0

Comparator input C0

Output of negative reference voltage

Input for an external negative reference voltage to the ADC
P9.0/ESICH0/ESITEST0/A8/C8 40

General-purpose digital I/O

ESI channel 0 sensor excitation output and signal input

ESI test signal 0

Analog input A8; comparator input C8
P9.1/ESICH1/ESITEST1/ A9/C9 41 General-purpose digital I/O

ESI channel 1 sensor excitation output and signal input

ESI test signal 1

Analog input A9

Comparator input C9
P9.2/ESICH2/ESITEST2/A10/C10 42 General-purpose digital I/O

ESI channel 2 sensor excitation output and signal input

ESI test signal 2

Analog input A10

Comparator input C10
P9.3/ESICH3/ESITEST3/A11/C11 43 General-purpose digital I/O

ESI channel 3 sensor excitation output and signal input

ESI test signal 3

Analog input A11

Comparator input C11
P9.4/ESICI0/A12/C12 44 General-purpose digital I/O

ESI channel 0 signal input to comparator

Analog input A12

Comparator input C12
P9.5/ESICI1/A13/C13 45 General-purpose digital I/O

ESI channel 1 signal input to comparator

Analog input A13

Comparator input C13
P9.6/ESICI2/A14/C14 46 General-purpose digital I/O

ESI channel 2 signal input to comparator

Analog input A14

Comparator input C14
P9.7/ESICI3/A15/C15 47 General-purpose digital I/O

ESI channel 3 signal input to comparator

Analog input A15

Comparator input C15
ESIDVCC 48 ESI Power supply
ESIDVSS 49 ESI Ground supply
ESICI 50 ESI Scan IF input to Comparator
ESICOM 51 ESI Common termination for Scan IF sensors
AVCC1 52 Analog power supply
AVSS3 53 Analog ground supply
PJ.7/HFXOUT 54 General-purpose digital I/O

Output terminal of crystal oscillator XT2
PJ.6/HFXIN 55 General-purpose digital I/O

Input terminal for crystal oscillator XT2
AVSS1 56 Analog ground supply
PJ.4/LFXIN 57 General-purpose digital I/O

Input terminal for crystal oscillator XT1
PJ.5/LFXOUT 58 General-purpose digital I/O

Output terminal of crystal oscillator XT1
AVSS2 59 Analog ground supply
P4.0/UCB1SIMO/UCB1SDA/MCLK 60 General-purpose digital I/O

USCI_B1: Slave in, master out (SPI mode)

USCI_B1: I2C data (I2C mode)

MCLK output

P4.1/UCB1SOMI/UCB1SCL/ACLK 61 General-purpose digital I/O

USCI_B1: Slave out, master in (SPI mode)

USCI_B1: I2C clock (I2C mode)

ACLK output
DVSS3 62 Digital ground supply
DVCC3 63 Digital power supply
P4.2/UCA0SIMO/UCA0TXD/ UCB1CLK 64 General-purpose digital I/O

USCI_A0: Slave in, master out (SPI mode)

USCI_A0: Transmit data (UART mode)

USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
Thermal pad Pad RGC package only. QFN package exposed thermal pad. TI recommends connection to VSS.

3.3 Pin Multiplexing

Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see Section 5.11.24.

3.4 Connection of Unused Pins

Table 3-2 lists the correct termination of all unused pins.

Table 3-2 Connection of Unused Pins(1)

PIN POTENTIAL COMMENT
AVCC DVCC
AVSS DVSS
Px.0 to Px.7 Open Switched to port function, output direction (PxDIR.n = 1)
R33/LCDCAP DVSS or DVCC If not used the pin can be tied to either supplies.
ESIDVCC DVCC
ESIDVSS DVSS
ESICOM Open
ESICI Open
RST/NMI DVCC or VCC 47-kΩ pullup or internal pullup selected with 2.2-nF (10-nF(2)) pulldown.
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK		 Open The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these should be switched to port function, output direction. When used as JTAG pins, these pins should remain open.
TEST Open This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection guidelines.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers. If JTAG or Spy-Bi-Wire access is not needed, up to a 10-nF pulldown capacitor may be used.