SLAS789D June   2014  – August 2018 MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR59891 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions – MSP430FR698x and MSP430FR698x1
      2. Table 4-2 Signal Descriptions – MSP430FR598x and MSP430FR598x1
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11 Typical Characteristics, Current Consumption per Module
    12. 5.12 Thermal Resistance Characteristics
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1 Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.13.2 Reset Timing
        1. Table 5-3 Reset Input
      3. 5.13.3 Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4 Wake-up Characteristics
        1. Table 5-9   Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.13.4.1    Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5 Peripherals
        1. 5.13.5.1 Digital I/Os
          1. Table 5-11 Digital Inputs
          2. Table 5-12 Digital Outputs
          3. 5.13.5.1.1  Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
          4. Table 5-13 Pin-Oscillator Frequency, Ports Px
          5. 5.13.5.1.2  Typical Characteristics, Pin-Oscillator Frequency
        2. 5.13.5.2 Timer_A and Timer_B
          1. Table 5-14 Timer_A
          2. Table 5-15 Timer_B
        3. 5.13.5.3 eUSCI
          1. Table 5-16 eUSCI (UART Mode) Clock Frequency
          2. Table 5-17 eUSCI (UART Mode)
          3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
          4. Table 5-19 eUSCI (SPI Master Mode)
          5. Table 5-20 eUSCI (SPI Slave Mode)
          6. Table 5-21 eUSCI (I2C Mode)
        4. 5.13.5.4 LCD Controller
          1. Table 5-22 LCD_C, Recommended Operating Conditions
          2. Table 5-23 LCD_C Electrical Characteristics
        5. 5.13.5.5 ADC
          1. Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions
          2. Table 5-25 12-Bit ADC, Timing Parameters
          3. Table 5-26 12-Bit ADC, Linearity Parameters With External Reference
          4. Table 5-27 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
          5. Table 5-28 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
          6. Table 5-29 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
          7. Table 5-30 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
          8. Table 5-31 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
          9. Table 5-32 12-Bit ADC, Temperature Sensor and Built-In V1/2
          10. Table 5-33 12-Bit ADC, External Reference
        6. 5.13.5.6 Reference
          1. Table 5-34 REF, Built-In Reference
        7. 5.13.5.7 Comparator
          1. Table 5-35 Comparator_E
        8. 5.13.5.8 Scan Interface
          1. Table 5-36 Extended Scan Interface, Port Drive, Port Timing
          2. Table 5-37 Extended Scan Interface, Sample Capacitor/Ri Timing
          3. Table 5-38 Extended Scan Interface, VCC/2 Generator
          4. Table 5-39 Extended Scan Interface, 12-Bit DAC
          5. Table 5-40 Extended Scan Interface, Comparator
          6. Table 5-41 Extended Scan Interface, ESICLK Oscillator and TSM Clock Signals
        9. 5.13.5.9 FRAM Controller
          1. Table 5-42 FRAM
      6. 5.13.6 Emulation and Debug
        1. Table 5-43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
        1. 6.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  FRAM
    8. 6.8  RAM
    9. 6.9  Tiny RAM
    10. 6.10 Memory Protection Unit Including IP Encapsulation
    11. 6.11 Peripherals
      1. 6.11.1  Digital I/O
      2. 6.11.2  Oscillator and Clock System (CS)
      3. 6.11.3  Power-Management Module (PMM)
      4. 6.11.4  Hardware Multiplier (MPY)
      5. 6.11.5  Real-Time Clock (RTC_C)
      6. 6.11.6  Watchdog Timer (WDT_A)
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  DMA Controller
      9. 6.11.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.11.10 Extended Scan Interface (ESI)
      11. 6.11.11 Timer_A TA0, Timer_A TA1
      12. 6.11.12 Timer_A TA2
      13. 6.11.13 Timer_A TA3
      14. 6.11.14 Timer_B TB0
      15. 6.11.15 ADC12_B
      16. 6.11.16 Comparator_E
      17. 6.11.17 CRC16
      18. 6.11.18 CRC32
      19. 6.11.19 AES256 Accelerator
      20. 6.11.20 True Random Seed
      21. 6.11.21 Shared Reference (REF_A)
      22. 6.11.22 LCD_C
      23. 6.11.23 Embedded Emulation
        1. 6.11.23.1 Embedded Emulation Module (EEM)
        2. 6.11.23.2 EnergyTrace++™ Technology
      24. 6.11.24 Input/Output Diagrams
        1. 6.11.24.1  Digital I/O Functionality – Ports P1 to P10
        2. 6.11.24.2  Capacitive Touch Functionality Ports P1 to P10 and PJ
        3. 6.11.24.3  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger
        4. 6.11.24.4  Port P1 (P1.4 to P1.7) Input/Output With Schmitt Trigger
        5. 6.11.24.5  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
        6. 6.11.24.6  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
        7. 6.11.24.7  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
        8. 6.11.24.8  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
        9. 6.11.24.9  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
        10. 6.11.24.10 Port P6 (P6.0 to P6.6) Input/Output With Schmitt Trigger
        11. 6.11.24.11 Port P6 (P6.7) Input/Output With Schmitt Trigger
        12. 6.11.24.12 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger
        13. 6.11.24.13 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
        14. 6.11.24.14 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
        15. 6.11.24.15 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
        16. 6.11.24.16 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
        17. 6.11.24.17 Port P10 (P10.0 to P10.2) Input/Output With Schmitt Trigger
        18. 6.11.24.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
        19. 6.11.24.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
        20. 6.11.24.20 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Memory
      1. 6.13.1 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
      2. 7.2.2 LCD_C Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
      3. 7.2.3 Extended Scan Interface (ESI) Peripheral
        1. 7.2.3.1 Overview
        2. 7.2.3.2 Design Requirements
        3. 7.2.3.3 Detailed Design Procedure
        4. 7.2.3.4 Layout Guidelines
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3 Recommended Operating Conditions

Typical data are based on VCC = 3.0 V, TA = 25°C unless otherwise noted.
MIN NOM MAX UNIT
VCC Supply voltage range applied at all DVCC, AVCC, and ESIDVCC pins(1)(2)(3) 1.8(6) 3.6 V
VSS Supply voltage applied at all DVSS, AVSS, and ESIDVSS pins 0 V
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 85 °C
CDVCC Capacitor value at DVCC and ESIDVCC (4) 1–20% µF
fSYSTEM Processor frequency (maximum MCLK frequency)(5) No FRAM wait states (NWAITSx = 0) 0 8(8) MHz
With FRAM wait states (NWAITSx = 1)(7) 0 16(9)
fACLK Maximum ACLK frequency 50 kHz
fSMCLK Maximum SMCLK frequency 16(9) MHz
(1) TI recommends powering the DVCC, AVCC, and ESIDVCC pins from the same source. At a minimum, during power up, power down, and device operation, the voltage difference between DVCC, AVCC, and ESIDVCC must not exceed the limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
(2) See Table 5-1 for additional important information.
(3) Modules may have a different supply voltage range specification. See the specification of each module in this data sheet.
(4) Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC and ESIDVCC pins.
(5) Modules may have a different maximum input clock specification. See the specification of each module in this data sheet.
(6) The minimum supply voltage is defined by the supervisor SVS levels. See Table 5-2 for the exact values.
(7) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always executed without wait states.
(8) DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted.
(9) DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted. If a clock sources with a larger typical value is used, the clock must be divided in the clock system.