SLASEV3A March 2020 – December 2020 MSP430FR6005 , MSP430FR6007
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Vsdhs | SDHS power domain supply voltage | Vsdhs = Vuss | 1.52 | 1.6 | 1.65 | V | |
Isdhs_product | Operating supply current into AVCC and DVCC | Includes PLL, PGA, SDHS, and DTC, modulator clock = 80 MHz, output data rate = 8 Msps | 5.2 | mA | |||
fmod | Modulator clock | 68 | 80 | MHz | |||
BWmod | Frequency at –3-dB SNR | Modulator clock = 80 MHz, modulator only (no filter is enabled) | 1.5 | MHz | |||
SNR | Signal-to-noise ratio | Bandwidth from 200 kHz to 1.5 MHz, PGA gain: a gain from the PGA gain table for the maximum SNR | 100mVpp ≤ Input signal level ≤ 1000 mVpp, PVCC = 3.0 V, fmod = 80 MHz, OSR = 20 | 45 | dB | ||
tMOD_Settle | SDHS settling time (PGA + modulator) | TM2 – TM1, AUTOSSDIS = 0, 1% of settled DC level | 40 | µs | |||
TM2 – TM1, AUTOSSDIS = 1, 1% of settled DC level | 40 | ||||||
DROUTsdhs | Output data rate | 8 | Msps |