SLASEF5B January   2019  – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics, Active Mode Supply Currents
    6. 8.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 8.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 8.11 Current Consumption per Module
    12. 8.12 Thermal Resistance Characteristics
    13. 8.13 Timing and Switching Characteristics
      1. 8.13.1  Power Supply Sequencing
        1. 8.13.1.1 Brownout and Device Reset Power Ramp Requirements
        2. 8.13.1.2 SVS
      2. 8.13.2  Reset Timing
        1. 8.13.2.1 Reset Input
      3. 8.13.3  Clock Specifications
        1. 8.13.3.1 Low-Frequency Crystal Oscillator, LFXT
        2. 8.13.3.2 High-Frequency Crystal Oscillator, HFXT
        3. 8.13.3.3 DCO
        4. 8.13.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.13.3.5 Module Oscillator (MODOSC)
      4. 8.13.4  Wake-up Characteristics
        1. 8.13.4.1 Wake-up Times From Low-Power Modes and Reset
        2. 8.13.4.2 Typical Wake-up Charges
        3. 8.13.4.3 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 8.13.5  Digital I/Os
        1. 8.13.5.1 Digital Inputs
        2. 8.13.5.2 Digital Outputs
        3. 8.13.5.3 Typical Characteristics, Digital Outputs
      6. 8.13.6  LEA
        1. 8.13.6.1 Low-Energy Accelerator (LEA) Performance
      7. 8.13.7  Timer_A and Timer_B
        1. 8.13.7.1 Timer_A
        2. 8.13.7.2 Timer_B
      8. 8.13.8  eUSCI
        1. 8.13.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.13.8.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams
        6. 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics
        7. 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams
        8. 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics
        9. 8.13.8.9 eUSCI (SPI Slave Mode) Timing Diagrams
      9. 8.13.9  Segment LCD Controller
        1. 8.13.9.1 LCD_C Recommended Operating Conditions
        2. 8.13.9.2 LCD_C Electrical Characteristics
      10. 8.13.10 ADC12_B
        1. 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions
        2. 8.13.10.2 12-Bit ADC, Timing Parameters
        3. 8.13.10.3 12-Bit ADC, Linearity Parameters
        4. 8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference
        5. 8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference
        6. 8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. 8.13.10.7 12-Bit ADC, External Reference
        8. 8.13.10.8 Temperature Sensor Typical Characteristics
      11. 8.13.11 Reference
        1. 8.13.11.1 REF, Built-In Reference
      12. 8.13.12 Comparator
        1. 8.13.12.1 Comparator_E
      13. 8.13.13 FRAM
        1. 8.13.13.1 FRAM Memory
      14. 8.13.14 USS
        1. 8.13.14.1 USS Recommended Operating Conditions
        2. 8.13.14.2 USS LDO
        3. 8.13.14.3 USSXTAL
        4. 8.13.14.4 USS HSPLL
        5. 8.13.14.5 USS SDHS
        6. 8.13.14.6 USS PHY Output Stage
        7. 8.13.14.7 USS PHY Input Stage, Multiplexer
        8. 8.13.14.8 USS_PGA
        9. 8.13.14.9 USS Bias Voltage Generator
      15. 8.13.15 Emulation and Debug
        1. 8.13.15.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Ultrasonic Sensing Solution (USS_A)
    4. 9.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 9.5  Operating Modes
      1. 9.5.1 Peripherals in Low-Power Modes
      2. 9.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 9.6  Interrupt Vector Table and Signatures
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  FRAM Controller A (FRCTL_A)
    10. 9.10 RAM
    11. 9.11 Tiny RAM
    12. 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 9.13 Peripherals
      1. 9.13.1  Digital I/O
      2. 9.13.2  Oscillator and Clock System (CS)
      3. 9.13.3  Power-Management Module (PMM)
      4. 9.13.4  Hardware Multiplier (MPY)
      5. 9.13.5  Real-Time Clock (RTC_C)
      6. 9.13.6  Measurement Test Interface (MTIF)
      7. 9.13.7  Watchdog Timer (WDT_A)
      8. 9.13.8  System Module (SYS)
      9. 9.13.9  DMA Controller
      10. 9.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 9.13.11 TA0, TA1, and TA4
      12. 9.13.12 TA2 and TA3
      13. 9.13.13 TB0
      14. 9.13.14 ADC12_B
      15. 9.13.15 USS_A
      16. 9.13.16 Comparator_E
      17. 9.13.17 CRC16
      18. 9.13.18 CRC32
      19. 9.13.19 AES256 Accelerator
      20. 9.13.20 True Random Seed
      21. 9.13.21 Shared Reference (REF)
      22. 9.13.22 LCD_C
      23. 9.13.23 Embedded Emulation
        1. 9.13.23.1 Embedded Emulation Module (EEM) (S Version)
        2. 9.13.23.2 EnergyTrace++ Technology
    14. 9.14 Input/Output Diagrams
      1. 9.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 9.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 9.14.3  Port P1 (P1.2 to P1.5) Input/Output With Schmitt Trigger
      4. 9.14.4  Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
      5. 9.14.5  Port P2 (P2.0 to P2.1) Input/Output With Schmitt Trigger
      6. 9.14.6  Port P2 (P2.2 to P2.3) Input/Output With Schmitt Trigger
      7. 9.14.7  Port P2 (P2.4 to P2.5) Input/Output With Schmitt Trigger
      8. 9.14.8  Port P2 (P2.6 to P2.7) Input/Output With Schmitt Trigger
      9. 9.14.9  Port P3 (P3.0) Input/Output With Schmitt Trigger
      10. 9.14.10 Port P3 (P3.1) Input/Output With Schmitt Trigger
      11. 9.14.11 Port P3 (P3.2) Input/Output With Schmitt Trigger
      12. 9.14.12 Port P3 (P3.3) Input/Output With Schmitt Trigger
      13. 9.14.13 Port P3 (P3.4 to P3.5) Input/Output With Schmitt Trigger
      14. 9.14.14 Port P3 (P3.6 to P3.7) Input/Output With Schmitt Trigger
      15. 9.14.15 Port P4 (P4.0) Input/Output With Schmitt Trigger
      16. 9.14.16 Port P4 (P4.1 to P4.7) Input/Output With Schmitt Trigger
      17. 9.14.17 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      18. 9.14.18 Port P6 (P6.0) Input/Output With Schmitt Trigger
      19. 9.14.19 Port P6 (P6.1 to P6.2) Input/Output With Schmitt Trigger
      20. 9.14.20 Port P6 (P6.3) Input/Output With Schmitt Trigger
      21. 9.14.21 Port P6 (P6.4) Input/Output With Schmitt Trigger
      22. 9.14.22 Port P6 (P6.5 and P6.7) Input/Output With Schmitt Trigger
      23. 9.14.23 Port P7 (P7.0) Input/Output With Schmitt Trigger
      24. 9.14.24 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      25. 9.14.25 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      26. 9.14.26 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 9.15 Device Descriptors (TLV)
    16. 9.16 Memory Map
      1. 9.16.1 Peripheral File Map
    17. 9.17 Identification
      1. 9.17.1 Revision Identification
      2. 9.17.2 Device Identification
      3. 9.17.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1  Power Supply and Bulk Capacitors
      2. 10.1.2  External Oscillator (HFXT and LFXT)
      3. 10.1.3  USS Oscillator (USSXT)
      4. 10.1.4  Transducer Connection to the USS Module
      5. 10.1.5  Charge Pump Control of Input Multiplexer
      6. 10.1.6  JTAG
      7. 10.1.7  Reset
      8. 10.1.8  Unused Pins
      9. 10.1.9  General Layout Recommendations
      10. 10.1.10 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC12_B Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Detailed Design Procedure
        4. 10.2.1.4 Layout Guidelines
      2. 10.2.2 LCD_C Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
    9. 11.9 Export Control Notice
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.13.9 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 9-11 lists the available DMA trigger assignments.

Table 9-11 DMA Trigger Assignments(1)
TRIGGER CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5
0 DMAREQ DMAREQ DMAREQ DMAREQ DMAREQ DMAREQ
1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG
2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG
3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG
4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG
5 TA2CCR0 CCIFG TA2CCR0 CCIFG TA2CCR0 CCIFG TA2CCR0 CCIFG TA2CCR0 CCIFG TA2CCR0 CCIFG
6 TA3CCR0 CCIFG TA3CCR0 CCIFG TA3CCR0 CCIFG TA3CCR0 CCIFG TA3CCR0 CCIFG TA3CCR0 CCIFG
7 TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG
8 TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG
9 TA4CCR0 CCIFG TA4CCR0 CCIFG TA4CCR0 CCIFG TA4CCR0 CCIFG TA4CCR0 CCIFG TA4CCR0 CCIFG
10 Reserved Reserved Reserved Reserved Reserved Reserved
11 AES Trigger 0 AES Trigger 0 AES Trigger 0 AES Trigger 0 AES Trigger 0 AES Trigger 0
12 AES Trigger 1 AES Trigger 1 AES Trigger 1 AES Trigger 1 AES Trigger 1 AES Trigger 1
13 AES Trigger 2 AES Trigger 2 AES Trigger 2 AES Trigger 2 AES Trigger 2 AES Trigger 2
14 UCA0RXIFG UCA0RXIFG UCA0RXIFG UCA2RXIFG UCA2RXIFG UCA2RXIFG
15 UCA0TXIFG UCA0TXIFG UCA0TXIFG UCA2TXIFG UCA2TXIFG UCA2TXIFG
16 UCA1RXIFG UCA1RXIFG UCA1RXIFG UCA3RXIFG UCA3RXIFG UCA3RXIFG
17 UCA1TXIFG UCA1TXIFG UCA1TXIFG UCA3TXIFG UCA3TXIFG UCA3TXIFG
18 UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)		 UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)		 UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)		 UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)		 UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)		 UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
19 UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)		 UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)		 UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)		 UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)		 UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)		 UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
20 UCB0RXIFG1 (I2C) UCB0RXIFG1 (I2C) UCB0RXIFG1 (I2C) UCB1RXIFG1 (I2C) UCB1RXIFG1 (I2C) UCB1RXIFG1 (I2C)
21 UCB0TXIFG1 (I2C) UCB0TXIFG1 (I2C) UCB0TXIFG1 (I2C) UCB1TXIFG1 (I2C) UCB1TXIFG1 (I2C) UCB1TXIFG1 (I2C)
22 UCB0RXIFG2 (I2C) UCB0RXIFG2 (I2C) UCB0RXIFG2 (I2C) UCB1RXIFG2 (I2C) UCB1RXIFG2 (I2C) UCB1RXIFG2 (I2C)
23 UCB0TXIFG2 (I2C) UCB0TXIFG2 (I2C) UCB0TXIFG2 (I2C) UCB1TXIFG2 (I2C) UCB1TXIFG2 (I2C) UCB1TXIFG2 (I2C)
24 UCB0RXIFG3 (I2C) UCB0RXIFG3 (I2C) UCB0RXIFG3 (I2C) UCB1RXIFG3 (I2C) UCB1RXIFG3 (I2C) UCB1RXIFG3 (I2C)
25 UCB0TXIFG3 (I2C) UCB0TXIFG3 (I2C) UCB0TXIFG3 (I2C) UCB1TXIFG3 (I2C) UCB1TXIFG3 (I2C) UCB1TXIFG3 (I2C)
26 ADC12 end of conversion ADC12 end of conversion ADC12 end of conversion ADC12 end of conversion ADC12 end of conversion ADC12 end of conversion
27 LEA Ready LEA Ready USS_A PPGTRIG USS_A PPGTRIG LEA Ready LEA Ready
28 Reserved Reserved Reserved Reserved Reserved Reserved
29 MPY ready MPY ready MPY ready MPY ready MPY ready MPY ready
30 DMA2IFG DMA0IFG DMA1IFG DMA5IFG DMA3IFG DMA4IFG
31 DMAE0 DMAE0 DMAE0 DMAE0 DMAE0 DMAE0
(1) If a reserved trigger source is selected, no trigger is generated.