SLASEF5 Data sheet

SLASEF5B January 2019 – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

PN|80
- MTQF010B

Thermal pad, mechanical data (Package|Pins)

Orderable Information

9.13.13 TB0

TB0 is a 16-bit timer and counter (Timer_B type) with seven capture/compare registers. TB0 can support multiple captures or compares, PWM outputs, and interval timing (see Table 9-17). TB0 has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 9-17 TB0 Signal Connections

INPUT PORT PIN	DEVICE INPUT SIGNAL	MODULE INPUT SIGNAL	MODULE BLOCK	MODULE OUTPUT SIGNAL	DEVICE OUTPUT SIGNAL	OUTPUT PORT PIN
P2.4, P4.6, P6.2	TB0CLK	TBCLK	Timer	N/A	N/A
	ACLK (internal)	ACLK
	SMCLK (internal)	SMCLK
P2.4, P4.6, P6.2	TB0CLK	INCLK
P3.0	TB0.0	CCI0A	CCR0	TB0	TB0.0	P3.0
P5.0	TB0.0	CCI0B				P5.0
	DVSS	GND				ADC12 (internal)⁽¹⁾ ADC12SHSx = {2}
	DVCC	V_CC
P3.1	TB0.1	CCI1A	CCR1	TB1	TB0.1	P3.1
	COUT (internal)	CCI1B				P5.1
	DVSS	GND				ADC12 (internal)⁽¹⁾ ADC12SHSx = {3}
	DVCC	V_CC
P3.7	TB0.2	CCI2A	CCR2	TB2	TB0.2	P3.7
	ACLK (internal)	CCI2B				P5.2
	DVSS	GND
	DVCC	V_CC
P5.3	TB0.3	CCI3A	CCR3	TB3	TB0.3	P5.3
P3.3	TB0.3	CCI3B				P3.3
	DVSS	GND
	DVCC	V_CC
P1.4	TB0.4	CCI4A	CCR4	TB4	TB0.4	P1.4
P4.1	TB0.4	CCI4B				P4.1
	DVSS	GND
	DVCC	V_CC
P1.5	TB0.5	CCI5A	CCR5	TB5	TB0.5	P1.5
P4.2	TB0.5	CCI5B				P4.2
	DVSS	GND
	DVCC	V_CC
PJ.3	TB0.6	CCI6A	CCR6	TB6	TB0.6	PJ.3
P3.6	TB0.6	CCI6B				P3.6
	DVSS	GND
	DVCC	V_CC

(1) Only on devices with ADC.