SLASEF5 Data sheet

SLASEF5B January 2019 – December 2021 MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

PN|80
- MTQF010B

Thermal pad, mechanical data (Package|Pins)

Orderable Information

9.13.12 TA2 and TA3

TA2 and TA3 are 16-bit timers and counters (Timer_A type) with two capture/compare registers each and with internal connections only. Each timer can support multiple captures or compares, PWM outputs, and interval timing (see Table 9-15 and Table 9-16). Each timer has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 9-15 TA2 Signal Connections

DEVICE INPUT SIGNAL	MODULE INPUT NAME	MODULE BLOCK	MODULE OUTPUT SIGNAL	DEVICE OUTPUT SIGNAL
COUT (internal)	TACLK	Timer	N/A
ACLK (internal)	ACLK
SMCLK (internal)	SMCLK
Reserved	INCLK
TA3 CCR0 output (internal)	CCI0A	CCR0	TA0	TA3 CCI0A input
ACLK (internal)	CCI0B
DVSS	GND
DVCC	V_CC
Reserved	CCI1A	CCR1	TA1	ADC12(internal)⁽¹⁾ ADC12SHSx = {5}
COUT (internal)	CCI1B			PPG Trigger (PPGTRIG) SAPH.PGCTL.TRSEL={2}
DVSS	GND
DVCC	V_CC

(1) Only on devices with ADC

Table 9-16 TA3 Signal Connections

DEVICE INPUT SIGNAL	MODULE INPUT NAME	MODULE BLOCK	MODULE OUTPUT SIGNAL	DEVICE OUTPUT SIGNAL
COUT (internal)	TACLK	Timer	N/A
ACLK (internal)	ACLK
SMCLK (internal)	SMCLK
Reserved	INCLK
TA2 CCR0 output (internal)	CCI0A	CCR0	TA0	TA2 CCI0A input
ACLK (internal)	CCI0B
DVSS	GND
DVCC	V_CC
Reserved	CCI1A	CCR1	TA1	ADC12(internal)⁽¹⁾ ADC12SHSx = {6}
COUT (internal)	CCI1B
DVSS	GND
DVCC	V_CC

(1) Only on devices with ADC