SLASEB7 Data sheet

SLASEB7D June 2017 – December 2020 MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

PZ|100
- MTQF013A

Thermal pad, mechanical data (Package|Pins)

PZ|100
- QFND428

Orderable Information

9.6 Interrupt Vector Table and Signatures

The interrupt vectors, the power-up start address, and signatures are in the address range 0FFFFh to 0FF80h. Figure 9-2 summarizes the content of this address range.

Figure 9-2 Interrupt Vectors, Signatures and Passwords

The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing to the start address of the application program.

The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 9-4 shows the device-specific interrupt vector locations.

The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if enabled by the corresponding signature).

The signatures start at 0FF80h and extend to higher addresses. Signatures are evaluated during device start-up. Table 9-5 shows the device-specific signature locations.

A JTAG password can be programmed starting from address 0FF88h and extending to higher addresses. The password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for the password. The length of the JTAG password depends on the JTAG signature.

See the chapter System Resets, Interrupts, and Operating Modes, System Control Module (SYS) in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.

Table 9-4 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE	INTERRUPT FLAG	INTERRUPT VECTOR REGISTER	SYSTEM INTERRUPT	WORD ADDRESS	PRIORITY
System Reset		SYSRSTIV⁽¹⁾	Reset	0FFFEh	Highest
Power up, brownout, supply supervisor	SVSHIFG
External reset, RST	PMMRSTIFG
Watchdog time-out (watchdog mode)	WDTIFG
WDT, FRCTL MPU, CS, PMM password violation	WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
FRAM uncorrectable bit error detection	UBDIFG
MPU segment violation	MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG
Software POR, BOR	PMMPORIFG, PMMBORIFG
System NMI		SYSSNIV⁽¹⁾	(Non)maskable⁽³⁾	0FFFCh
Vacant memory access⁽²⁾	VMAIFG
JTAG mailbox	JMBINIFG, JMBOUTIFG
FRAM access time error	ACCTEIFG
FRAM write protection error	WPIFG
FRAM bit error detection	CBDIFG, UBDIFG
MPU segment violation	MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG
User NMI		SYSUNIV⁽¹⁾	(Non)maskable⁽³⁾	0FFFAh
External NMI	NMIIFG
Oscillator fault	OFIFG
LEA RAM access conflict	DACCESSIFG
Comparator_E	CEIFG, CEIIFG, CERDYIFG	CEIV⁽¹⁾	Maskable	0FFF8h
TB0	TB0CCR0 CCIFG		Maskable	0FFF6h
TB0	TB0CCR1 CCIFG to TB0CCR6 CCIFG, TB0CTL.TBIFG	TB0IV⁽¹⁾	Maskable	0FFF4h
Watchdog timer (interval timer mode)	WDTIFG		Maskable	0FFF2h
eUSCI_A0 receive or transmit	UCRXIFG, UCTXIFG (SPI mode)	UCA0IV⁽¹⁾	Maskable	0FFF0h
eUSCI_A0 receive or transmit	UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode)	UCA0IV⁽¹⁾	Maskable	0FFF0h
eUSCI_B0 receive or transmit	UCRXIFG, UCTXIFG (SPI mode)	UCB0IV⁽¹⁾	Maskable	0FFEEh
eUSCI_B0 receive or transmit	UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I²C mode)	UCB0IV⁽¹⁾	Maskable	0FFEEh
ADC12_B⁽⁴⁾	ADC12IFG0 to ADC12IFG31, ADC12LOIFG, ADC12INIFG, ADC12HIIFG, ADC12RDYIFG, ADC21OVIFG, ADC12TOVIFG	ADC12IV⁽¹⁾	Maskable	0FFECh
TA0	TA0CCR0 CCIFG		Maskable	0FFEAh
TA0	TA0CCR1 CCIFG, TA0CCR2 CCIFG, TA0CTL.TAIFG	TA0IV⁽¹⁾	Maskable	0FFE8h
eUSCI_A1 receive or transmit	UCRXIFG, UCTXIFG (SPI mode)	UCA1IV⁽¹⁾	Maskable	0FFE6h
eUSCI_A1 receive or transmit	UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode)	UCA1IV⁽¹⁾	Maskable	0FFE6h
DMA	DMA0CTL.DMAIFG, DMA1CTL.DMAIFG, DMA2CTL.DMAIFG	DMAIV⁽¹⁾	Maskable	0FFE4h
TA1	TA1CCR0 CCIFG		Maskable	0FFE2h
TA1	TA1CCR1 CCIFG, TA1CCR2 CCIFG, TA1CTL.TAIFG	TA1IV⁽¹⁾	Maskable	0FFE0h
I/O port P1	P1IFG.0 to P1IFG.7	P1IV⁽¹⁾	Maskable	0FFDEh
TA2	TA2CCR0 CCIFG		Maskable	0FFDCh
TA2	TA2CCR1 CCIFG, TA2CTL.TAIFG	TA2IV⁽¹⁾	Maskable	0FFDAh
I/O port P2	P2IFG.0 to P2IFG.7	P2IV⁽¹⁾	Maskable	0FFD8h
TA3	TA3CCR0 CCIFG		Maskable	0FFD6h
TA3	TA3CCR1 CCIFG, TA3CTL.TAIFG	TA3IV⁽¹⁾	Maskable	0FFD4h
I/O port P3	P3IFG.0 to P3IFG.7	P3IV⁽¹⁾	Maskable	0FFD2h
I/O port P4	P4IFG.0 to P4IFG.7	P4IV⁽¹⁾	Maskable	0FFD0h
LCD_C	LCDNOCAPIFG, LCDBLKOFFIFG, LCDBLKONIFG, LCDFRMIFG	LCDCIV⁽¹⁾	Maskable	0FFCEh
RTC_C	RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG	RTCIV⁽¹⁾	Maskable	0FFCCh
AES	AESRDYIFG		Maskable	0FFCAh
TA4	TA4CCR0 CCIFG		Maskable	0FFC8h
TA4	TA4CCR1 CCIFG, TA4CTL.TAIFG	TA4IV⁽¹⁾	Maskable	0FFC6h
I/O port P5	P5IFG.0 to P5IFG.7	P5IV⁽¹⁾	Maskable	0FFC4h
I/O port P6	P6IFG.0 to P6IFG.7	P6IV⁽¹⁾	Maskable	0FFC2h
eUSCI_A2 receive or transmit	UCRXIFG, UCTXIFG (SPI mode)	UCA2IV⁽¹⁾	Maskable	0FFC0h
eUSCI_A2 receive or transmit	UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode)	UCA2IV⁽¹⁾	Maskable	0FFC0h
eUSCI_A3 receive or transmit	UCRXIFG, UCTXIFG (SPI mode)	UCA3IV⁽¹⁾	Maskable	0FFBEh
eUSCI_A3 receive or transmit	UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode)	UCA3IV⁽¹⁾	Maskable	0FFBEh
eUSCI_B1 receive or transmit	UCRXIFG, UCTXIFG (SPI mode)	UCB1IV⁽¹⁾	Maskable	0FFBCh
eUSCI_B1 receive or transmit	UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I²C mode)	UCB1IV⁽¹⁾	Maskable	0FFBCh
I/O port P7	P7IFG.0 to P7IFG.7	P7IV⁽¹⁾	Maskable	0FFBAh
I/O port P8	P8IFG.0 to P8IFG.7	P8IV⁽¹⁾	Maskable	0FFB8h
I/O port P9	P9IFG.0 to P9IFG.7	P9IV⁽¹⁾	Maskable	0FFB6h
LEA	CMDIFG, SDIIFG, OORIFG, TIFG, COVLIFG	LEAIV⁽¹⁾	Maskable	0FFB4h
UUPS	PTMOUT, PREQIG	IIDX⁽¹⁾	Maskable	0FFB2h
HSPLL	PLLUNLOCK	IIDX⁽¹⁾	Maskable	0FFB0h
SAPH	DATAERR, TMFTO, SEQDN, PNGDN	IIDX⁽¹⁾	Maskable	0FFAEh
SDHS	OVF, ACQDONE, SSTRG, DTRDY, WINHI, WINLO	IIDX⁽¹⁾	Maskable	0FFACh	Lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space.

(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.

(4) Only on devices with ADC, otherwise reserved.

Table 9-5 Signatures

SIGNATURE	WORD ADDRESS
IP Encapsulation Signature2	0FF8Ah
IP Encapsulation Signature1⁽¹⁾	0FF88h
BSL Signature2	0FF86h
BSL Signature1	0FF84h
JTAG Signature2	0FF82h
JTAG Signature1	0FF80h

(1) Must not contain 0AAAAh if used as the JTAG password.