SLAS734G April   2011  – April 2016 MSP430G2203 , MSP430G2233 , MSP430G2303 , MSP430G2333 , MSP430G2403 , MSP430G2433 , MSP430G2533

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Current (Into VCC)
    6. 5.6  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Typical Characteristics, Low-Power Mode Supply Currents
    8. 5.8  Thermal Resistance Characteristics
    9. 5.9  Schmitt-Trigger Inputs, Ports Px
    10. 5.10 Leakage Current, Ports Px
    11. 5.11 Outputs, Ports Px
    12. 5.12 Output Frequency, Ports Px
    13. 5.13 Typical Characteristics - Outputs
    14. 5.14 Pin-Oscillator Frequency - Ports Px
    15. 5.15 Typical Characteristics - Pin-Oscillator Frequency
    16. 5.16 POR, BOR
    17. 5.17 Main DCO Characteristics
    18. 5.18 DCO Frequency
    19. 5.19 Calibrated DCO Frequencies, Tolerance
    20. 5.20 Wake-up Times From Lower-Power Modes (LPM3, LPM4)
    21. 5.21 Typical Characteristics, DCO Clock Wake-up Time From LPM3 or LPM4
    22. 5.22 Crystal Oscillator, XT1, Low-Frequency Mode
    23. 5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24 Timer_A
    25. 5.25 USCI (UART Mode)
    26. 5.26 USCI (SPI Master Mode)
    27. 5.27 USCI (SPI Slave Mode)
    28. 5.28 USCI (I2C Mode)
    29. 5.29 10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x33 Only)
    30. 5.30 10-Bit ADC, Built-In Voltage Reference (MSP430G2x33 Only)
    31. 5.31 10-Bit ADC, External Reference (MSP430G2x33 Only)
    32. 5.32 10-Bit ADC, Timing Parameters (MSP430G2x33 Only)
    33. 5.33 10-Bit ADC, Linearity Parameters (MSP430G2x33 Only)
    34. 5.34 10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x33 Only)
    35. 5.35 Flash Memory
    36. 5.36 RAM
    37. 5.37 JTAG and Spy-Bi-Wire Interface
    38. 5.38 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1 Oscillator and System Clock
      2. 6.9.2 Calibration Data Stored in Information Memory Segment A
      3. 6.9.3 Brownout
      4. 6.9.4 Digital I/O
      5. 6.9.5 WDT+ Watchdog Timer
      6. 6.9.6 Timer_A3 (TA0, TA1)
      7. 6.9.7 Universal Serial Communications Interface (USCI)
      8. 6.9.8 ADC10 (MSP430G2x33 Only)
      9. 6.9.9 Peripheral File Map
    10. 6.10 I/O Port Diagrams
      1. 6.10.1 Port P1 Pin Diagram: P1.0 to P1.2, Input/Output With Schmitt Trigger
      2. 6.10.2 Port P1 Pin Diagram: P1.3, Input/Output With Schmitt Trigger
      3. 6.10.3 Port P1 Pin Diagram: P1.4, Input/Output With Schmitt Trigger
      4. 6.10.4 Port P1 Pin Diagram: P1.5 to P1.7, Input/Output With Schmitt Trigger
      5. 6.10.5 Port P2 Pin Diagram: P2.0 to P2.5, Input/Output With Schmitt Trigger
      6. 6.10.6 Port P2 Pin Diagram: P2.6, Input/Output With Schmitt Trigger
      7. 6.10.7 Port P2 Pin Diagram: P2.7, Input/Output With Schmitt Trigger
      8. 6.10.8 Port P3 Pin Diagram: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB and PW28 Package Only)
  7. 7Device and Documentation Support
    1. 7.1 Getting Started and Next Steps
    2. 7.2 Device Nomenclature
    3. 7.3 Tools and Software
    4. 7.4 Documentation Support
    5. 7.5 Related Links
    6. 7.6 Community Resources
    7. 7.7 Trademarks
    8. 7.8 Electrostatic Discharge Caution
    9. 7.9 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Detailed Description

6.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers (see Figure 6-1).

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 slas000-040.gif Figure 6-1 Integrated CPU Registers

6.2 Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 6-1 lists examples of the three types of instruction formats. Table 6-2 lists the address modes.

Table 6-1 Instruction Word Formats

INSTRUCTION FORMAT EXAMPLE OPERATION
Dual operands, source-destination ADD R4,R5 R4 + R5 → R5
Single operands, destination only CALL R8 PC → (TOS), R8 → PC
Relative jump, unconditional or conditional JNE Jump-on-equal bit = 0

Table 6-2 Address Mode Descriptions

ADDRESS MODE S(1) D SYNTAX EXAMPLE OPERATION
Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 → R11
Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6)
Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) → M(TONI)
Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) → M(TCDAT)
Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)
Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 M(R10) → R11
R10 + 2 → R10
Immediate ✓ MOV #X,TONI MOV #45,TONI #45 → M(TONI)
(1) S = source, D = destination

6.3 Operating Modes

These microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

Software can configure the following operating modes:

  • Active mode (AM)
    • All clocks are active
  • Low-power mode 0 (LPM0)
    • CPU is disabled
    • ACLK and SMCLK remain active, MCLK is disabled
  • Low-power mode 1 (LPM1)
    • CPU is disabled
    • ACLK and SMCLK remain active, MCLK is disabled
    • DC generator of the DCO is disabled if DCO not used in active mode
  • Low-power mode 2 (LPM2)
    • CPU is disabled
    • MCLK and SMCLK are disabled
    • DC generator of the DCO remains enabled
    • ACLK remains active
  • Low-power mode 3 (LPM3)
    • CPU is disabled
    • MCLK and SMCLK are disabled
    • DC generator of the DCO is disabled
    • ACLK remains active
  • Low-power mode 4 (LPM4)
    • CPU is disabled
    • ACLK is disabled
    • MCLK and SMCLK are disabled
    • DC generator of the DCO is disabled
    • Crystal oscillator is stopped

6.4 Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are in the address range 0FFFFh to 0FFC0h (see Table 6-3). The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (at address 0FFFEh) contains 0FFFFh (for example, if the flash is not programmed), the CPU goes into LPM4 immediately after power-up.

Table 6-3 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power up
External reset
Watchdog Timer+
Flash key violation
PC out of range(1)		 PORIFG
RSTIFG
WDTIFG
KEYV(2)		 Reset 0FFFEh 31, highest
NMI
Oscillator fault
Flash memory access violation		 NMIIFG
OFIFG
ACCVIFG(2)		 (non)-maskable(6)
(non)-maskable
(non)-maskable		 0FFFCh 30
Timer1_A3 TACCR0 CCIFG(3) maskable 0FFFAh 29
Timer1_A3 TACCR2 TACCR1 CCIFG, TAIFG(2)(3) maskable 0FFF8h 28
0FFF6h 27
Watchdog Timer+ WDTIFG maskable 0FFF4h 26
Timer0_A3 TACCR0 CCIFG(3) maskable 0FFF2h 25
Timer0_A3 TACCR2 TACCR1 CCIFG, TAIFG (4)(3) maskable 0FFF0h 24
USCI_A0, USCI_B0 receive
USCI_B0 I2C status		 UCA0RXIFG, UCB0RXIFG(2)(4) maskable 0FFEEh 23
USCI_A0, USCI_B0 transmit
USCI_B0 I2C receive or transmit		 UCA0TXIFG, UCB0TXIFG(2)(5) maskable 0FFECh 22
ADC10
(MSP430G2x33 only)		 ADC10IFG(3) maskable 0FFEAh 21
0FFE8h 20
I/O Port P2 (up to eight flags) P2IFG.0 to P2IFG.7(2)(3) maskable 0FFE6h 19
I/O Port P1 (up to eight flags) P1IFG.0 to P1IFG.7(2)(3) maskable 0FFE4h 18
0FFE2h 17
0FFE0h 16
See (7) 0FFDEh 15
See (8) 0FFDEh to 0FFC0h 14 to 0, lowest
(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges.
(2) Multiple source flags
(3) Interrupt flags are in the module.
(4) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
(5) In UART or SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
(6) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(7) This location is used as bootloader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h) disables the erasure of the flash if an invalid password is supplied.
(8) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if necessary.

6.5 Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

Legend
rw Bit can be read and written.
rw-0, rw-1 Bit can be read and written. It is reset or set by PUC.
rw-(0), rw-(1) Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Figure 6-2 Interrupt Enable Register 1 (Address = 00h)
7 6 5 4 3 2 1 0
ACCVIE NMIIE OFIE WDTIE
rw-0 rw-0 rw-0 rw-0

Table 6-4 Interrupt Enable Register 1 Description

Bit Field Type Reset Description
5 ACCVIE RW 0h Flash access violation interrupt enable
4 NMIIE RW 0h (Non)maskable interrupt enable
1 OFIE RW 0h Oscillator fault interrupt enable
0 WDTIE RW 0h Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode.
Figure 6-3 Interrupt Enable Register 2 (Address = 01h)
7 6 5 4 3 2 1 0
  UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
  rw-0 rw-0 rw-0 rw-0

Table 6-5 Interrupt Enable Register 2 Description

Bit Field Type Reset Description
3 UCB0TXIE RW 0h USCI_B0 transmit interrupt enable
2 UCB0RXIE RW 0h USCI_B0 receive interrupt enable
1 UCA0TXIE RW 0h USCI_A0 transmit interrupt enable
0 UCA0RXIE RW 0h USCI_A0 receive interrupt enable
Figure 6-4 Interrupt Flag Register 1 (Address = 02h)
7 6 5 4 3 2 1 0
NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw-0 rw-(0) rw-(1) rw-1 rw-(0)

Table 6-6 Interrupt Flag Register 1 Description

Bit Field Type Reset Description
4 NMIIFG RW 0h Set by the RST/NMI pin
3 RSTIFG RW 0h External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
2 PORIFG RW 1h Power-On Reset interrupt flag. Set on VCC power-up.
1 OFIFG RW 1h Flag set on oscillator fault.
0 WDTIFG RW 0h Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
Figure 6-5 Interrupt Flag Register 2 (Address = 03h)
7 6 5 4 3 2 1 0
  UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG
  rw-1 rw-0 rw-1 rw-0

Table 6-7 Interrupt Flag Register 2 Description

Bit Field Type Reset Description
3 UCB0TXIFG RW 0h USCI_B0 transmit interrupt flag
2 UCB0RXIFG RW 1h USCI_B0 receive interrupt flag
1 UCA0TXIFG RW 1h USCI_A0 transmit interrupt flag
0 UCA0RXIFG RW 0h USCI_A0 receive interrupt flag

6.6 Memory Organization

Table 6-8 summarizes the memory map.

Table 6-8 Memory Organization

MSP430G2233
MSP430G2203		 MSP430G2333
MSP430G2303		 MSP430G2433
MSP430G2403		 MSP430G2533
Memory Size 2KB 4KB 8KB 16KB
Main: interrupt vector Flash FFFFh to FFC0h FFFFh to FFC0h FFFFh to FFC0h FFFFh to FFC0h
Main: code memory Flash FFFFh to F800h FFFFh to F000h FFFFh to E000h FFFFh to C000h
Information memory Size 256 byte 256 byte 256 byte 256 byte
Flash 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h
RAM Size 256 byte 256 byte 512 byte 512 byte
02FFh to 0200h 02FFh to 0200h 03FFh to 0200h 03FFh to 0200h
Peripherals 16-bit 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h
8-bit 0FFh to 010h 0FFh to 010h 0FFh to 010h 0FFh to 010h
8-bit SFR 0Fh to 00h 0Fh to 00h 0Fh to 00h 0Fh to 00h

6.7 Bootloader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory through the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Programming With the Bootloader User's Guide (SLAU319). Table 6-9 lists the BSL function pins.

Table 6-9 BSL Function Pins

BSL FUNCTION 20-PIN PW PACKAGE
20-PIN N PACKAGE		 28-PIN PW PACKAGE 32-PIN RHB PACKAGE
Data transmit 3 - P1.1 3 - P1.1 1 - P1.1
Data receive 7 - P1.5 7 - P1.5 5 - P1.5

6.8 Flash Memory

The flash memory can be programmed through the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

  • Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size.
  • Segments 0 to n may be erased in one step, or each segment may be individually erased.
  • Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also called information memory.
  • Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.

6.9 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be managed using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

6.9.1 Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turnon clock source and stabilizes in less than 1 µs. The basic clock module provides the following clock signals:

  • Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
  • Main clock (MCLK), the system clock used by the CPU.
  • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.

The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.

6.9.2 Calibration Data Stored in Information Memory Segment A

Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure (see Table 6-10 and Table 6-11).

Table 6-10 Tags Used by the ADC Calibration Tags

NAME ADDRESS VALUE DESCRIPTION
TAG_DCO_30 0x10F6 0x01 DCO frequency calibration at VCC = 3 V and TA = 30°C
TAG_ADC10_1 0x10DA 0x10 ADC10_1 calibration tag
TAG_EMPTY – 0xFE Identifier for empty memory areas

Table 6-11 Labels Used by the ADC Calibration Tags

LABEL ADDRESS OFFSET SIZE CONDITION AT CALIBRATION
CAL_ADC_25T85 0x0010 word INCHx = 1010b, REF2_5 = 1, TA = 85°C
CAL_ADC_25T30 0x000E word INCHx = 1010b, REF2_5 = 1, TA = 30°C
CAL_ADC_25VREF_FACTOR 0x000C word REF2_5 = 1, TA = 30°C, IVREF+ = 1 mA
CAL_ADC_15T85 0x000A word INCHx = 1010b, REF2_5 = 0, TA = 85°C
CAL_ADC_15T30 0x0008 word INCHx = 1010b, REF2_5 = 0, TA = 30°C
CAL_ADC_15VREF_FACTOR 0x0006 word REF2_5 = 0, TA = 30°C, IVREF+ = 0.5 mA
CAL_ADC_OFFSET 0x0004 word External VREF = 1.5 V, fADC10CLK = 5 MHz
CAL_ADC_GAIN_FACTOR 0x0002 word External VREF = 1.5 V, fADC10CLK = 5 MHz
CAL_BC1_1MHZ 0x0009 byte  –
CAL_DCO_1MHZ 0x0008 byte  –
CAL_BC1_8MHZ 0x0007 byte  –
CAL_DCO_8MHZ 0x0006 byte  –
CAL_BC1_12MHZ 0x0005 byte  –
CAL_DCO_12MHZ 0x0004 byte  –
CAL_BC1_16MHZ 0x0003 byte  –
CAL_DCO_16MHZ 0x0002 byte  –

6.9.3 Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.

6.9.4 Digital I/O

Up to three 8-bit I/O ports are implemented:

  • All individual I/O bits are independently programmable.
  • Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible.
  • Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available).
  • Read/write access to port-control registers is supported by all instructions.
  • Each I/O has an individually programmable pullup or pulldown resistor.
  • Each I/O has an individually programmable pin oscillator enable bit to enable low-cost capacitive touch detection.

6.9.5 WDT+ Watchdog Timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.

6.9.6 Timer_A3 (TA0, TA1)

Timer0_A3 and Timer1_A3 are 16-bit timers/counters with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-12 and Table 6-13). Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-12 Timer0_A3 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER
PW20, N20 PW28 RHB32 PW20, N20 PW28 RHB32
P1.0-2 P1.0-2 P1.0-31 TACLK TACLK Timer NA
ACLK ACLK
SMCLK SMCLK
PinOsc PinOsc PinOsc TACLK INCLK
P1.1-3 P1.1-3 P1.1-1 TA0.0 CCI0A CCR0 TA0 P1.1-3 P1.1-3 P1.1-1
ACLK CCI0B P1.5-7 P1.5-7 P1.5-5
VSS GND – P3.4-15 P3.4-14
VCC VCC
P1.2-4 P1.2-4 P1.2-2 TA0.1 CCI1A CCR1 TA1 P1.2-4 P1.2-4 P1.2-2
CAOUT CCI1B P1.6-14 P1.6-22 P1.6-21
VSS GND P2.6-19 P2.6-27 P2.6-26
VCC VCC – P3.5-19 P3.5-18
– P3.0-9 P3.0-7 TA0.2 CCI2A CCR2 TA2 – P3.0-9 P3.0-7
PinOsc PinOsc PinOsc TA0.2 CCI2B – P3.6-20 P3.6-19
VSS GND
VCC VCC

Table 6-13 Timer1_A3 Signal Connections

INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER
PW20, N20 PW28 RHB32 PW20, N20 PW28 RHB32
– P3.7-21 P3.7-20 TACLK TACLK Timer NA
ACLK ACLK
SMCLK SMCLK
– P3.7-21 P3.7-20 TACLK INCLK
P2.0-8 P2.0-10 P2.0-9 TA1.0 CCI0A CCR0 TA0 P2.0-8 P2.0-10 P2.0-9
P2.3-11 P2.3-16 P2.3-12 TA1.0 CCI0B P2.3-11 P2.3-16 P2.3-15
VSS GND P3.1-8 P3.1-6
VCC VCC
P2.1-9 P2.1-11 P2.1-10 TA1.1 CCI1A CCR1 TA1 P2.1-9 P2.1-11 P2.1-10
P2.2-10 P2.2-12 P2.2-11 TA1.1 CCI1B P2.2-10 P2.2-12 P2.2-11
VSS GND P3.2-13 P3.2-12
VCC VCC
P2.4-12 P2.4-17 P2.4-16 TA1.2 CCI2A CCR2 TA2 P2.4-12 P2.4-17 P2.4-16
P2.5-13 P2.5-18 P2.5-17 TA1.2 CCI2B P2.5-13 P2.5-18 P2.5-17
VSS GND P3.3-14 P3.3-13
VCC VCC

6.9.7 Universal Serial Communications Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baud rate detection (LIN), and IrDA. Not all packages support the USCI functionality.

USCI_A0 provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.

USCI_B0 provides support for SPI (3-pin or 4-pin) and I2C.

6.9.8 ADC10 (MSP430G2x33 Only)

The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion result handling, allowing ADC samples to be converted and stored without any CPU intervention.

6.9.9 Peripheral File Map

Table 6-14 lists the registers that support word access. Table 6-15 that support byte access.

Table 6-14 Peripherals With Word Access

MODULE REGISTER DESCRIPTION ACRONYM OFFSET
ADC10 (MSP430G2x33 only) ADC data transfer start address ADC10SA 1BCh
ADC memory ADC10MEM 1B4h
ADC control register 1 ADC10CTL1 1B2h
ADC control register 0 ADC10CTL0 1B0h
Timer1_A3 Capture/compare register TA1CCR2 0196h
Capture/compare register TA1CCR1 0194h
Capture/compare register TA1CCR0 0192h
Timer_A register TA1R 0190h
Capture/compare control TA1CCTL2 0186h
Capture/compare control TA1CCTL1 0184h
Capture/compare control TA1CCTL0 0182h
Timer_A control TA1CTL 0180h
Timer_A interrupt vector TA1IV 011Eh
Timer0_A3 Capture/compare register TA0CCR2 0176h
Capture/compare register TA0CCR1 0174h
Capture/compare register TA0CCR0 0172h
Timer_A register TA0R 0170h
Capture/compare control TA0CCTL2 0166h
Capture/compare control TA0CCTL1 0164h
Capture/compare control TA0CCTL0 0162h
Timer_A control TA0CTL 0160h
Timer_A interrupt vector TA0IV 012Eh
Flash Memory Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
Watchdog Timer+ Watchdog timer control WDTCTL 0120h

Table 6-15 Peripherals With Byte Access

MODULE REGISTER DESCRIPTION ACRONYM OFFSET
USCI_B0 USCI_B0 transmit buffer UCB0TXBUF 06Fh
USCI_B0 receive buffer UCB0RXBUF 06Eh
USCI_B0 status UCB0STAT 06Dh
USCI B0 I2C Interrupt enable UCB0CIE 06Ch
USCI_B0 bit rate control 1 UCB0BR1 06Bh
USCI_B0 bit rate control 0 UCB0BR0 06Ah
USCI_B0 control 1 UCB0CTL1 069h
USCI_B0 control 0 UCB0CTL0 068h
USCI_B0 I2C slave address UCB0SA 011Ah
USCI_B0 I2C own address UCB0OA 0118h
USCI_A0 USCI_A0 transmit buffer UCA0TXBUF 067h
USCI_A0 receive buffer UCA0RXBUF 066h
USCI_A0 status UCA0STAT 065h
USCI_A0 modulation control UCA0MCTL 064h
USCI_A0 baud rate control 1 UCA0BR1 063h
USCI_A0 baud rate control 0 UCA0BR0 062h
USCI_A0 control 1 UCA0CTL1 061h
USCI_A0 control 0 UCA0CTL0 060h
USCI_A0 IrDA receive control UCA0IRRCTL 05Fh
USCI_A0 IrDA transmit control UCA0IRTCTL 05Eh
USCI_A0 auto baud rate control UCA0ABCTL 05Dh
ADC10 (MSP430G2x33 only) ADC analog enable 0 ADC10AE0 04Ah
ADC analog enable 1 ADC10AE1 04Bh
ADC data transfer control register 1 ADC10DTC1 049h
ADC data transfer control register 0 ADC10DTC0 048h
Basic Clock System+ Basic clock system control 3 BCSCTL3 053h
Basic clock system control 2 BCSCTL2 058h
Basic clock system control 1 BCSCTL1 057h
DCO clock frequency control DCOCTL 056h
Port P3
(28-pin PW and 32-pin RHB only)		 Port P3 selection 2. pin P3SEL2 043h
Port P3 resistor enable P3REN 010h
Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 selection 2 P2SEL2 042h
Port P2 resistor enable P2REN 02Fh
Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 selection 2 P1SEL2 041h
Port P1 resistor enable P1REN 027h
Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Function SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h

6.10 I/O Port Diagrams

6.10.1 Port P1 Pin Diagram: P1.0 to P1.2, Input/Output With Schmitt Trigger

Figure 6-6 shows the port diagram. Table 6-16 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p1_012_las734.gif Figure 6-6 Port P1 (P1.0 to P1.2) Diagram

Table 6-16 Port P1 (P1.0 to P1.2) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x
(INCH.y = 1)(2)
P1.0/ 0 P1.x (I/O) I: 0; O: 1 0 0 0
TA0CLK/ TA0.TACLK 0 1 0 0
ACLK/ ACLK 1 1 0 0
A0(2)/ A0 X X X 1 (y = 0)
Pin Osc Capacitive sensing X 0 1 0
P1.1/ 1 P1.x (I/O) I: 0; O: 1 0 0 0
TA0.0/ TA0.0 1 1 0 0
TA0.CCI0A 0 1 0 0
UCA0RXD/ UCA0RXD from USCI 1 1 0
UCA0SOMI/ UCA0SOMI from USCI 1 1 0
A1(2)/ A1 X X X 1 (y = 1)
Pin Osc Capacitive sensing X 0 1 0
P1.2/ 2 P1.x (I/O) I: 0; O: 1 0 0 0
TA0.1/ TA0.1 1 1 0 0
TA0.CCI1A 0 1 0 0
UCA0TXD/ UCA0TXD from USCI 1 1 0
UCA0SIMO/ UCA0SIMO from USCI 1 1 0
A2(2)/ A2 X X X 1 (y = 2)
Pin Osc Capacitive sensing X 0 1 0
(1) X = don't care
(2) MSP430G2x33 devices only

6.10.2 Port P1 Pin Diagram: P1.3, Input/Output With Schmitt Trigger

Figure 6-7 shows the port diagram. Table 6-17 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p1_3_las734.gif Figure 6-7 Port P1 (P1.3) Diagram

Table 6-17 Port P1 (P1.3) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x
(INCH.y = 1)(2)
P1.3/ 3 P1.x (I/O) I: 0; O: 1 0 0 0
ADC10CLK(2)/ ADC10CLK 1 1 0 0
A3(2)/ A3 X X X 1 (y = 3)
VREF-(2)/ VREF- X X X 1
VEREF-(2)/ VEREF- X X X 1
Pin Osc Capacitive sensing X 0 1 0

6.10.3 Port P1 Pin Diagram: P1.4, Input/Output With Schmitt Trigger

Figure 6-8 shows the port diagram. Table 6-18 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p1_4_las734.gif Figure 6-8 Port P1 (P1.4) Diagram

Table 6-18 Port P1 (P1.4) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x
(INCH.y = 1)(2)		 JTAG Mode
P1.4/ 4 P1.x (I/O) I: 0; O: 1 0 0 0 0
SMCLK/ SMCLK 1 1 0 0 0
UCB0STE/ UCB0STE(1)(2) from USCI 1 1 0 0
UCA0CLK/ UCA0CLK(1)(2) from USCI 1 1 0 0
VREF+(2)/ VREF+ X X X 1 0
VEREF+(2)/ VEREF+ X X X 1 0
A4(2)/ A4 X X X 1 (y = 4) 0
TCK/ TCK X X X 0 1
Pin Osc Capacitive sensing X 0 1 0 0
(1) The pin direction is controlled by the USCI module.
(2) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected.

6.10.4 Port P1 Pin Diagram: P1.5 to P1.7, Input/Output With Schmitt Trigger

Figure 6-9 shows the port diagram. Table 6-19 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p1_567_las734.gif Figure 6-9 Port P1 (P1.5 to P1.7) Diagram

Table 6-19 Port P1 (P1.5 to P1.7) Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x
(INCH.y = 1)(2)		 JTAG Mode
P1.5/ 5 P1.x (I/O) I: 0; O: 1 0 0 0 0
TA0.0/ TA0.0 1 1 0 0 0
UCB0CLK/ UCB0CLK(1)(2) from USCI 1 1 0 0
UCA0STE/ UCA0STE(1)(2) from USCI 1 1 0 0
A5(2)/ A5 X X X 1 (y = 5) 0
TMS TMS X X X 0 1
Pin Osc Capacitive sensing X 0 1 0 0
P1.6/ 6 P1.x (I/O) I: 0; O: 1 0 0 0 0
TA0.1/ TA0.1 1 1 0 0 0
UCB0SOMI/ UCB0SOMI from USCI 1 1 0 0
UCB0SCL/ UCB0SCL from USCI 1 1 0 0
A6(2)/ A6 X X X 1 (y = 6) 0
TDI/TCLK/ TDI/TCLK X X X 0 1
Pin Osc Capacitive sensing X 0 1 0 0
P1.7/ 7 P1.x (I/O) I: 0; O: 1 0 0 0 0
UCB0SIMO/ UCB0SIMO from USCI 1 1 0 0
UCB0SDA/ UCB0SDA from USCI 1 1 0 0
A7(2)/ A7 X X X 1 (y = 7) 0
TDO/TDI/ TDO/TDI X X X 0 1
Pin Osc Capacitive sensing X 0 1 0 0
(1) The pin direction is controlled by the USCI module.
(2) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected.

6.10.5 Port P2 Pin Diagram: P2.0 to P2.5, Input/Output With Schmitt Trigger

Figure 6-10 shows the port diagram. Table 6-20 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p2_012345_las734.gif Figure 6-10 Port P2 (P2.0 to P2.5) Diagram

Table 6-20 Port P2 (P2.0 to P2.5) Pin Functions

PIN NAME (P2.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P2DIR.x P2SEL.x P2SEL2.x
P2.0/ 0 P2.x (I/O) I: 0; O: 1 0 0
TA1.0/ Timer1_A3.CCI0A 0 1 0
Timer1_A3.TA0 1 1 0
Pin Osc Capacitive sensing X 0 1
P2.1/ 1 P2.x (I/O) I: 0; O: 1 0 0
TA1.1/ Timer1_A3.CCI1A 0 1 0
Timer1_A3.TA1 1 1 0
Pin Osc Capacitive sensing X 0 1
P2.2/ 2 P2.x (I/O) I: 0; O: 1 0 0
TA1.1/ Timer1_A3.CCI1B 0 1 0
Timer1_A3.TA1 1 1 0
Pin Osc Capacitive sensing X 0 1
P2.3/ 3 P2.x (I/O) I: 0; O: 1 0 0
TA1.0/ Timer1_A3.CCI0B 0 1 0
Timer1_A3.TA0 1 1 0
Pin Osc Capacitive sensing X 0 1
P2.4/ 4 P2.x (I/O) I: 0; O: 1 0 0
TA1.2/ Timer1_A3.CCI2A 0 1 0
Timer1_A3.TA2 1 1 0
Pin Osc Capacitive sensing X 0 1
P2.5/ 5 P2.x (I/O) I: 0; O: 1 0 0
TA1.2/ Timer1_A3.CCI2B 0 1 0
Timer1_A3.TA2 1 1 0
Pin Osc Capacitive sensing X 0 1

6.10.6 Port P2 Pin Diagram: P2.6, Input/Output With Schmitt Trigger

Figure 6-11 shows the port diagram. Table 6-21 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p2_6_las734.gif Figure 6-11 Port P2 (P2.6) Diagram

Table 6-21 Port P2 (P2.6) Pin Functions

PIN NAME (P2.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P2DIR.x P2SEL.6
P2SEL.7		 P2SEL2.6
P2SEL2.7
XIN 6 XIN 0 1
1		 0
0
P2.6 P2.x (I/O) I: 0; O: 1 0
X		 0
0
TA0.1 Timer0_A3.TA1 1 1
0		 0
0
Pin Osc Capacitive sensing X 0
X		 1
X

6.10.7 Port P2 Pin Diagram: P2.7, Input/Output With Schmitt Trigger

Figure 6-12 shows the port diagram. Table 6-22 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p2_7_las734.gif Figure 6-12 Port P2 (P2.7) Diagram

Table 6-22 Port P2 (P2.7) Pin Functions

PIN NAME (P2.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P2DIR.x P2SEL.6
P2SEL.7		 P2SEL2.6
P2SEL2.7
XOUT/ 7 XOUT 1 1
1		 0
0
P2.7/ P2.x (I/O) I: 0; O: 1 0
X		 0
0
Pin Osc Capacitive sensing X 0
X		 1
X

6.10.8 Port P3 Pin Diagram: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB and PW28 Package Only)

Figure 6-13 shows the port diagram. Table 6-23 summarizes the selection of the pin functions.

MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303 MSP430G2203 p3_01234567_las734.gif Figure 6-13 Port P3 (P3.0 to P3.7) Diagram (RHB and PW28 Package Only)

Table 6-23 Port P3 (P3.0 to P3.7) Pin Functions (RHB and PW28 Package Only)

PIN NAME (P3.x) x FUNCTION CONTROL BITS OR SIGNALS(1)
P3DIR.x P3SEL.x P3SEL2.x
P3.0/ 0 P3.x (I/O) I: 0; O: 1 0 0
TA0.2/ Timer0_A3.CCI2A 0 1 0
Timer0_A3.TA2 1 1 0
Pin Osc Capacitive sensing X 0 1
P3.1/ 1 P3.x (I/O) I: 0; O: 1 0 0
TA1.0/ Timer1_A3.TA0 1 1 0
Pin Osc Capacitive sensing X 0 1
P3.2/ 2 P3.x (I/O) I: 0; O: 1 0 0
TA1.1/ Timer1_A3.TA1 1 1 0
Pin Osc Capacitive sensing X 0 1
P3.3/ 3 P3.x (I/O) I: 0; O: 1 0 0
TA1.2/ Timer1_A3.TA2 1 1 0
Pin Osc Capacitive sensing X 0 1
P3.4/ 4 P3.x (I/O) I: 0; O: 1 0 0
TA0.0/ Timer0_A3.TA0 1 1 0
Pin Osc Capacitive sensing X 0 1
P3.5/ 5 P3.x (I/O) I: 0; O: 1 0 0
TA0.1/ Timer0_A3.TA1 1 1 0
Pin Osc Capacitive sensing X 0 1
P3.6/ 6 P3.x (I/O) I: 0; O: 1 0 0
TA0.2/ Timer0_A3.TA2 1 1 0
Pin Osc Capacitive sensing X 0 1
P3.7/ 7 P3.x (I/O) I: 0; O: 1 0 0
TA1CLK/ Timer1_A3.TACLK 0 1 0
Pin Osc Capacitive sensing X 0 1