SLAS734G April 2011 – April 2016 MSP430G2203 , MSP430G2233 , MSP430G2303 , MSP430G2333 , MSP430G2403 , MSP430G2433 , MSP430G2533
PRODUCTION DATA.
The TI MSP family of ultra-low-power microcontrollers consists of several devices that feature different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in less than 1 µs.
The MSP430G2x03 and MSP430G2x33 devices are ultra-low-power mixed-signal microcontrollers with built-in 16-bit timers, up to 24 I/O capacitive-touch enabled pins, and built-in communication capability using the USCI. In addition, the MSP430G2x33 family members have a 10-bit ADC. See Section 3 for configuration details.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system.
PART NUMBER | PACKAGE | BODY SIZE(2) |
---|---|---|
MSP430G2533IRHB | VQFN (32) | 5 mm × 5 mm |
MSP430G2533IPW | TSSOP (28) | 9.7 mm × 4.4 mm |
TSSOP (20) | 6.5 mm × 4.4 mm | |
MSP430G2533IN | PDIP (20) | 24.33 mm × 6.35 mm |
Figure 1-1 shows the functional block diagram of the MSP430G2x33 MCUs.
NOTE:
Port P3 is available on 28-pin and 32-pin devices only.Figure 1-2 shows the functional block diagram of the MSP430G2x03 MCUs.
NOTE:
Port P3 is available on 28-pin and 32-pin devices only.Changes from May 2, 2013 to April 27, 2016
Table 3-1 compares the available family members.
DEVICE | BSL | EEM | FLASH (KB) |
RAM (B) |
Timer_A | ADC10 CHANNELS | USCI_A0, USCI_B0 | CLOCK | I/O | PACKAGE |
---|---|---|---|---|---|---|---|---|---|---|
MSP430G2533 | 1 | 1 | 16 | 512 | 2x TA3 | 8 | 1 | LF, DCO, VLO | 24 | 32-QFN |
24 | 28-TSSOP | |||||||||
16 | 20-TSSOP | |||||||||
16 | 20-PDIP | |||||||||
MSP430G2433 | 1 | 1 | 8 | 512 | 2x TA3 | 8 | 1 | LF, DCO, VLO | 24 | 32-QFN |
24 | 28-TSSOP | |||||||||
16 | 20-TSSOP | |||||||||
16 | 20-PDIP | |||||||||
MSP430G2333 | 1 | 1 | 4 | 256 | 2x TA3 | 8 | 1 | LF, DCO, VLO | 24 | 32-QFN |
24 | 28-TSSOP | |||||||||
16 | 20-TSSOP | |||||||||
16 | 20-PDIP | |||||||||
MSP430G2233 | 1 | 1 | 2 | 256 | 2x TA3 | 8 | 1 | LF, DCO, VLO | 24 | 32-QFN |
24 | 28-TSSOP | |||||||||
16 | 20-TSSOP | |||||||||
16 | 20-PDIP | |||||||||
MSP430G2403 | 1 | 1 | 8 | 512 | 2x TA3 | – | 1 | LF, DCO, VLO | 24 | 32-QFN |
24 | 28-TSSOP | |||||||||
16 | 20-TSSOP | |||||||||
16 | 20-PDIP | |||||||||
MSP430G2303 | 1 | 1 | 4 | 256 | 2x TA3 | – | 1 | LF, DCO, VLO | 24 | 32-QFN |
24 | 28-TSSOP | |||||||||
16 | 20-TSSOP | |||||||||
16 | 20-PDIP | |||||||||
MSP430G2203 | 1 | 1 | 2 | 256 | 2x TA3 | – | 1 | LF, DCO, VLO | 24 | 32-QFN |
24 | 28-TSSOP | |||||||||
16 | 20-TSSOP | |||||||||
16 | 20-PDIP |
For information about other devices in this family of products or related products, see the following links.
Figure 4-1 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 20-pin N or PW package.
NOTE:
ADC10 is available on MSP430G2x33 devices only.NOTE:
The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.Figure 4-2 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 28-pin PW package.
NOTE:
ADC10 is available on MSP430G2x33 devices only.Figure 4-3 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 32-pin RHB package.
NOTE:
ADC10 is available on MSP430G2x33 devices only.Table 4-1 describes the signals.
TERMINAL | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | NO. | ||||
PW20, N20 | PW28 | RHB32 | |||
P1.0/ | 2 | 2 | 31 | I/O | General-purpose digital I/O pin |
TA0CLK/ | Timer0_A, clock signal TACLK input | ||||
ACLK/ | ACLK signal output | ||||
A0 | ADC10 analog input A0(1) | ||||
P1.1/ | 3 | 3 | 1 | I/O | General-purpose digital I/O pin |
TA0.0/ | Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit | ||||
UCA0RXD/ | USCI_A0 receive data input in UART mode | ||||
UCA0SOMI/ | USCI_A0 slave data out/master in SPI mode | ||||
A1 | ADC10 analog input A1(1) | ||||
P1.2/ | 4 | 4 | 2 | I/O | General-purpose digital I/O pin |
TA0.1/ | Timer0_A, capture: CCI1A input, compare: Out1 output | ||||
UCA0TXD/ | USCI_A0 transmit data output in UART mode | ||||
UCA0SIMO/ | USCI_A0 slave data in/master out in SPI mode | ||||
A2 | ADC10 analog input A2(1) | ||||
P1.3/ | 5 | 5 | 3 | I/O | General-purpose digital I/O pin |
ADC10CLK/ | ADC10, conversion clock output(1) | ||||
A3/ | ADC10 analog input A3(1) | ||||
VREF-/VEREF- | ADC10 negative reference voltage (1) | ||||
P1.4/ | 6 | 6 | 4 | I/O | General-purpose digital I/O pin |
SMCLK/ | SMCLK signal output | ||||
UCB0STE/ | USCI_B0 slave transmit enable | ||||
UCA0CLK/ | USCI_A0 clock input/output | ||||
A4/ | ADC10 analog input A4(1) | ||||
VREF+/VEREF+ | ADC10 positive reference voltage(1) | ||||
TCK | JTAG test clock, input terminal for device programming and test | ||||
P1.5/ | 7 | 7 | 5 | I/O | General-purpose digital I/O pin |
TA0.0/ | Timer0_A, compare: Out0 output / BSL receive | ||||
UCB0CLK/ | USCI_B0 clock input/output | ||||
UCA0STE/ | USCI_A0 slave transmit enable | ||||
A5/ | ADC10 analog input A5(1) | ||||
TMS | JTAG test mode select, input terminal for device programming and test | ||||
P1.6/ | 14 | 22 | 21 | I/O | General-purpose digital I/O pin |
TA0.1/ | Timer0_A, compare: Out1 output | ||||
A6/ | ADC10 analog input A6(1) | ||||
UCB0SOMI/ | USCI_B0 slave out/master in SPI mode, | ||||
UCB0SCL/ | USCI_B0 SCL I2C clock in I2C mode | ||||
TDI/TCLK | JTAG test data input or test clock input during programming and test | ||||
P1.7/ | 15 | 23 | 22 | I/O | General-purpose digital I/O pin |
A7/ | ADC10 analog input A7(1) | ||||
UCB0SIMO/ | USCI_B0 slave in/master out in SPI mode | ||||
UCB0SDA/ | USCI_B0 SDA I2C data in I2C mode | ||||
TDO/TDI | JTAG test data output terminal or test data input during programming and test(3) | ||||
P2.0/ | 8 | 10 | 9 | I/O | General-purpose digital I/O pin |
TA1.0 | Timer1_A, capture: CCI0A input, compare: Out0 output | ||||
P2.1/ | 9 | 11 | 10 | I/O | General-purpose digital I/O pin |
TA1.1 | Timer1_A, capture: CCI1A input, compare: Out1 output | ||||
P2.2/ | 10 | 12 | 11 | I/O | General-purpose digital I/O pin |
TA1.1 | Timer1_A, capture: CCI1B input, compare: Out1 output | ||||
P2.3/ | 11 | 16 | 15 | I/O | General-purpose digital I/O pin |
TA1.0 | Timer1_A, capture: CCI0B input, compare: Out0 output | ||||
P2.4/ | 12 | 17 | 16 | I/O | General-purpose digital I/O pin |
TA1.2 | Timer1_A, capture: CCI2A input, compare: Out2 output | ||||
P2.5/ | 13 | 18 | 17 | I/O | General-purpose digital I/O pin |
TA1.2 | Timer1_A, capture: CCI2B input, compare: Out2 output | ||||
XIN/ | 19 | 27 | 26 | I/O | Input terminal of crystal oscillator |
P2.6/ | General-purpose digital I/O pin | ||||
TA0.1 | Timer0_A, compare: Out1 output | ||||
XOUT/ | 18 | 26 | 25 | I/O | Output terminal of crystal oscillator(2) |
P2.7 | General-purpose digital I/O pin | ||||
P3.0/ | - | 9 | 7 | I/O | General-purpose digital I/O pin |
TA0.2 | Timer0_A, capture: CCI2A input, compare: Out2 output | ||||
P3.1/ | - | 8 | 6 | I/O | General-purpose digital I/O pin |
TA1.0 | Timer1_A, compare: Out0 output | ||||
P3.2/ | - | 13 | 12 | I/O | General-purpose digital I/O pin |
TA1.1 | Timer1_A, compare: Out1 output | ||||
P3.3/ | - | 14 | 13 | I/O | General-purpose digital I/O |
TA1.2 | Timer1_A, compare: Out2 output | ||||
P3.4/ | - | 15 | 14 | I/O | General-purpose digital I/O |
TA0.0 | Timer0_A, compare: Out0 output | ||||
P3.5/ | - | 19 | 18 | I/O | General-purpose digital I/O |
TA0.1 | Timer0_A, compare: Out1 output | ||||
P3.6/ | - | 20 | 19 | I/O | General-purpose digital I/O |
TA0.2 | Timer0_A, compare: Out2 output | ||||
P3.7/ | - | 21 | 20 | I/O | General-purpose digital I/O |
TA1CLK | Timer1_A, clock signal TACLK input | ||||
RST/ | 16 | 24 | 23 | I | Reset |
NMI/ | Nonmaskable interrupt input | ||||
SBWTDIO | Spy-Bi-Wire test data input/output during programming and test | ||||
TEST/ | 17 | 25 | 24 | I | Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. |
SBWTCK | Spy-Bi-Wire test clock input during programming and test | ||||
AVCC | NA | NA | 29 | NA | Analog supply voltage |
DVCC | 1 | 1 | 30 | NA | Digital supply voltage |
DVSS | 20 | 28 | 27, 28 | NA | Ground reference |
NC | NA | NA | 8, 32 | NA | Not connected |
QFN Pad | NA | NA | Pad | NA | QFN package pad connection to VSS recommended. |