SLASEN5 October   2017 MSP432E401Y

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 GPIO Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended DC Operating Conditions
    5. 5.5  Recommended GPIO Operating Characteristics
    6. 5.6  Recommended Fast GPIO Pad Operating Conditions
    7. 5.7  Recommended Slow GPIO Pad Operating Conditions
    8. 5.8  GPIO Current Restrictions
    9. 5.9  I/O Reliability
    10. 5.10 Current Consumption
    11. 5.11 Peripheral Current Consumption
    12. 5.12 LDO Regulator Characteristics
    13. 5.13 Power Dissipation
    14. 5.14 Thermal Resistance Characteristics, 128-Pin PDT (TQFP) Package
    15. 5.15 Timing and Switching Characteristics
      1. 5.15.1  Load Conditions
      2. 5.15.2  Power Supply Sequencing
        1. 5.15.2.1 Power and Brownout
          1. 5.15.2.1.1 VDDA Levels
          2. 5.15.2.1.2 VDD Levels
          3. 5.15.2.1.3 VDDC Levels
          4. 5.15.2.1.4 VDD Glitch Response
          5. 5.15.2.1.5 VDD Droop Response
      3. 5.15.3  Reset Timing
      4. 5.15.4  Clock Specifications
        1. 5.15.4.1 PLL Specifications
          1. 5.15.4.1.1 PLL Configuration
        2. 5.15.4.2 PIOSC Specifications
        3. 5.15.4.3 Low-Frequency Oscillator Specifications
        4. 5.15.4.4 Hibernation Low-Frequency Oscillator Specifications
        5. 5.15.4.5 Main Oscillator Specifications
        6. 5.15.4.6 Main Oscillator Specification WIth ADC
        7. 5.15.4.7 System Clock Characteristics With USB Operation
      5. 5.15.5  Sleep Modes
      6. 5.15.6  Hibernation Module
      7. 5.15.7  Flash Memory
      8. 5.15.8  EEPROM
      9. 5.15.9  Input/Output Pin Characteristics
        1. 5.15.9.1 Types of I/O Pins and ESD Protection
          1. 5.15.9.1.1 Hibernate WAKE pin
          2. 5.15.9.1.2 Nonpower I/O Pins
      10. 5.15.10 External Peripheral Interface (EPI)
      11. 5.15.11 Analog-to-Digital Converter (ADC)
      12. 5.15.12 Synchronous Serial Interface (SSI)
      13. 5.15.13 Inter-Integrated Circuit (I2C) Interface
      14. 5.15.14 Ethernet Controller
        1. 5.15.14.1 DC Characteristics
        2. 5.15.14.2 Clock Characteristics for Ethernet
        3. 5.15.14.3 AC Characteristics
      15. 5.15.15 Universal Serial Bus (USB) Controller
      16. 5.15.16 Analog Comparator
      17. 5.15.17 Pulse-Width Modulator (PWM)
      18. 5.15.18 Emulation and Debug
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Arm Cortex-M4F Processor Core
      1. 6.3.1 Processor Core
      2. 6.3.2 System Timer (SysTick)
      3. 6.3.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.3.4 System Control Block (SCB)
      5. 6.3.5 Memory Protection Unit (MPU)
      6. 6.3.6 Floating-Point Unit (FPU)
    4. 6.4 On-Chip Memory
      1. 6.4.1 SRAM
      2. 6.4.2 Flash Memory
      3. 6.4.3 ROM
      4. 6.4.4 EEPROM
      5. 6.4.5 Memory Map
    5. 6.5 Peripherals
      1. 6.5.1  External Peripheral Interface (EPI)
      2. 6.5.2  Cyclical Redundancy Check (CRC)
      3. 6.5.3  Advanced Encryption Standard (AES) Accelerator
      4. 6.5.4  Data Encryption Standard (DES) Accelerator
      5. 6.5.5  Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5) Accelerator
      6. 6.5.6  Serial Communications Peripherals
        1. 6.5.6.1 Ethernet MAC and PHY
        2. 6.5.6.2 Controller Area Network (CAN)
        3. 6.5.6.3 Universal Serial Bus (USB)
        4. 6.5.6.4 Universal Asynchronous Receiver/Transmitter (UART)
        5. 6.5.6.5 Inter-Integrated Circuit (I2C)
        6. 6.5.6.6 Quad Synchronous Serial Interface (QSSI)
      7. 6.5.7  System Integration
        1. 6.5.7.1 Direct Memory Access (DMA)
        2. 6.5.7.2 System Control and Clocks
        3. 6.5.7.3 Programmable Timers
        4. 6.5.7.4 Capture Compare PWM (CCP) Pins
        5. 6.5.7.5 Hibernation (HIB) Module
        6. 6.5.7.6 Watchdog Timers
        7. 6.5.7.7 Programmable GPIOs
      8. 6.5.8  Advanced Motion Control
        1. 6.5.8.1 Pulse Width Modulation (PWM)
        2. 6.5.8.2 Quadrature Encoder With Index (QEI) Module
      9. 6.5.9  Analog
        1. 6.5.9.1 ADC
        2. 6.5.9.2 Analog Comparators
      10. 6.5.10 JTAG and Arm Serial Wire Debug
      11. 6.5.11 Peripheral Memory Map
    6. 6.6 Identification
    7. 6.7 Boot Modes
  7. 7Applications, Implementation, and Layout
    1. 7.1 System Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Community Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • Core
    • 120-MHz Arm® Cortex®-M4F Processor Core With Floating-Point Unit (FPU)
  • Connectivity
    • Ethernet MAC: 10/100 Ethernet MAC With Integrated Ethernet PHY
    • Ethernet PHY: PHY With IEEE 1588 PTP Hardware Support
    • Universal Serial Bus (USB): USB 2.0 OTG, Host, or Device With ULPI Interface Option and Link Power Management (LPM)
    • Eight Universal Asynchronous Receivers/Transmitters (UARTs), Each With Independently Clocked Transmitter and Receiver
    • Four Quad Synchronous Serial Interface (QSSI): With Bi-, Quad-, and Advanced-SSI Support
    • Ten Inter-Integrated Circuit (I2C) Modules With High-Speed Mode Support
    • Two CAN 2.0 A and B Controllers: Multicast Shared Serial-Bus Standard
  • Memories
    • 1024KB of Flash Memory With 4-Bank Configuration Supports an Independent Code Protection for Each Bank
    • 256KB of SRAM With Single-Cycle Access, Provides Nearly 2-GB/s Memory Bandwidth at 120-MHz Clock Frequency
    • 6KB EEPROM: 500-kwrite per 2 Page Block, Leveling, Lock Protection
    • Internal ROM: Loaded With SimpleLink™ SDK Software
      • Peripheral Driver Library
      • Bootloader
    • External Peripheral Interface (EPI): 8-, 16-, or 32-Bit Dedicated Parallel Interface to Access External Devices and Memory (SDRAM, Flash, or SRAM)
  • Security
    • Advanced Encryption Standard (AES): Hardware Accelerated Data Encryption and Decryption Based on 128-, 192-, and 256-Bit Keys
    • Data Encryption Standard (DES): Hardware Accelerated Data Encryption and Decryption Supported by Block Cipher Implementation With 168-Bit Effective Key Length
    • Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5): Advanced Hash Engine That Supports SHA-1, SHA-2, and MD5 Hash Computation
    • Cyclical Redundancy Check (CRC) Hardware
    • Tamper: Support for Four Tamper Inputs and Configurable Tamper Event Response
  • Analog
    • Two 12-Bit SAR-Based ADC Modules, Each Supports Up to 2 Million Samples per Second (2 Msps)
    • Three Independent Analog Comparator Controllers
    • 16 Digital Comparators
  • System Management
    • JTAG and Serial Wire Debug (SWD): One JTAG Module With Integrated Arm SWD Provides a Means of Accessing and Controlling Design-for-Test Features Such as I/O Pin Observation and Control, Scan Testing, and Debugging.
  • Development Kits and Software (See Tools and Software)
    • SimpleLink™ MSP-EXP432E401Y LaunchPad™ Development Kit
    • SimpleLink MSP432E4 Software Development Kit (SDK)
  • Package Information
    • Package: 128-Pin TQFP (PDT)
    • Extended Operating Temperature (Ambient) Range: –40°C to 105°C

1.2 Applications

  • Industrial Ethernet Gateway
  • Industrial Smart Gateway
  • Zone Controllers for Building Automation
  • Factory Automation Data Collectors and Gateway
  • Data Concentrators for Grid Infrastructure
  • Wireless to Ethernet Gateway

1.3 Description

The SimpleLink MSP432E401Y Arm® Cortex®-M4F microcontrollers provide top performance and advanced integration. The product family is positioned for cost-effective applications requiring significant control processing and connectivity capabilities.

The MSP432E401Y microcontrollers integrate a large variety of rich communication features to enable a new class of highly connected designs with the ability to allow critical real-time control between performance and power. The microcontrollers feature integrated communication peripherals along with other high-performance analog and digital functions to offer a strong foundation for many different target uses, spanning from human-machine interface (HMI) to networked system management controllers.

In addition, the MSP432E401Y microcontrollers offer the advantages of widely available development tools, system-on-chip (SoC) infrastructure, and a large user community for Arm-based microcontrollers. Additionally, these microcontrollers use the Arm Thumb®-compatible Thumb-2® instruction set to reduce memory requirements and, thereby, cost. When using the SimpleLink MSP432™ SDK, the MSP432E401Y microcontroller is code compatible with all members of the extensive SimpleLink family, providing flexibility to fit precise needs.

The MSP432E401Y device is part of the SimpleLink microcontroller (MCU) platform, which consists of Wi-Fi®, Bluetooth® low energy, Sub-1 GHz, Ethernet, Zigbee, Thread, and host MCUs, which all share a common, easy-to-use development environment with a single core software development kit (SDK) and rich tool set. A one-time integration of the SimpleLink platform enables you to add any combination of the portfolio's devices into your design, allowing 100 percent code reuse when your design requirements change. For more information, visit www.ti.com/simplelink.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
MSP432E401YTPDT TQFP (128) 14 mm × 14 mm
(1) For more information, see Section 9, Mechanical, Packaging, and Orderable Information.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram.

MSP432E401Y msp432e401y-high-level-block-diagram.gif Figure 1-1 MSP432E401Y Functional Block Diagram