SLASF93A October   2023  – July 2024 MSPM0C1103-Q1 , MSPM0C1104-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 ADC
      1. 7.11.1 Electrical Characteristics
      2. 7.11.2 Switching Characteristics
      3. 7.11.3 Linearity Parameters
      4. 7.11.4 Typical Connection Diagram
    12. 7.12 Temperature Sensor
    13. 7.13 VREF
      1. 7.13.1 Voltage Characteristics
      2. 7.13.2 Electrical Characteristics
    14. 7.14 I2C
      1. 7.14.1 I2C Characteristics
      2. 7.14.2 I2C Filter
      3. 7.14.3 I2C Timing Diagram
    15. 7.15 SPI
      1. 7.15.1 SPI
      2. 7.15.2 SPI Timing Diagrams
    16. 7.16 UART
    17. 7.17 TIMx
    18. 7.18 Windowed Watchdog Characteristics
    19. 7.19 Emulation and Debug
      1. 7.19.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0C110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 CRC
    16. 8.16 UART
    17. 8.17 SPI
    18. 8.18 I2C
    19. 8.19 WWDT
    20. 8.20 Timers (TIMx)
    21. 8.21 Device Analog Connections
    22. 8.22 Input/Output Diagrams
    23. 8.23 Serial Wire Debug Interface
    24. 8.24 Device Factory Constants
    25. 8.25 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Pin Attributes

The following table describes the functions available on every pin for each device package.

Note: Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) that lets users configure the desired Pin Function using the PINCM.PF control bits.
Table 6-1 Pin Attributes
PINCMx PIN FUNCTION PIN NUMBER I/O Structure

PIN NAME

 ANALOG DIGITAL (1)

20 VSSOP

20 WQFN

 16 SOT 8 SOT 8 WSON
N/A VDD 6 4 5 4 4 Power
N/A VSS 7 5 6 3 3 Power
1 PA0 BEEP [2] / I2C0_SDA [3] / TIMG8_C0 [4] / SPI0_CS1 [5]/ FCC_IN [6]/ TIMA_FAL1 [7] 4 2 3 5 5 5V Tolerant Open-Drain
2 PA1 I2C0_SCL [2] / TIM8_C0 [3] / HFCLK_IN [4]/ TIMA0_C1 [5] 5 3 4 2 2 5V Tolerant Open-Drain
N/A NRST Reset
3 PA2 TIMG8_C1[2] / SPI0_CS0[3] / TIMA0_C0[4] / TIMG8_IDX[5] 8 6 7 - - Standard
5 PA4 TIMA0_C0N[2] / SPI0_POCI[3]/ LFCLK_IN[4]/ HFCLK_IN[5] / TIMA0_C1N[6] 9 7 - - - Standard
7 PA6 TIMG14__C1[2] / SPI0_SCK[3] / TIMA0_C1[4] / TIMG14_C2[5] / SPI0_CS0[6] / TIMA_FAL0[7] 10 8 8 - - Standard
12 PA11 SPI0_SCK[2] / I2C0_SCL[3] / TIMA_FAL0[4] 11 9 - - - Standard
17 PA16 A8 TIMA0_C1N[2] / SPI0_POCI[3] / TIMG14_C0[4] / FCC_IN[5] 12 10 - - - Standard
18 PA17 A9 UART0_TX[2] / TIMA0_C0N[3] / SPI0_SCK[4] / TIMA0_C2[5] / SPI0_CS1[6] / TIMA0_C3[7] 13 11 9 - - Standard
19 PA18 A7 UART0_RX[2] / SPI0_PICO[3] / TIMA0_C1N[4] / CLK_OUT[5] / TIMA0_C3[6] / TIMA0_C3N[7] 14 12 10 - - Standard
20 PA19 SWDIO[2] / SPI0_SCK[3] / SPI0_POCI[4] / TIMA0_C2[5] / TIMG14_C0[6] / UART0_CTS[7] 15 13 11 6 6 Standard
21 PA20 A6 SWCLK[2] / TIMA_FAL1[3] / SPI0_PICO[4] / TIMA0_C2N[5] / TIMA0_C0[6] / UART0_RTS[7] 16 14 12 7 7 Standard
23 PA22 A4 UART0_RX[2] / SPI0_POCI[3] / UART0_RTS[4] / CLK_OUT[5] / TIMA0_C1[6] 17 15 13 - - Standard
24 PA23 UART0_TX[2] / SPI0_CS3[3] / TIMG14_C0[4] / UART0_CTS[5] / TIMA0_C3[6] / TIMG14_C1[7] 18 16 14 - - Standard
25 PA24 A3 SPI0_CS2[2] / TIMG14_C1[3] / UART0_RTS[4] / TIMG14_C2[5] / TIMA0_C3N[6] / UART0_RX[7] 19 17 15 8 8 Standard
26 PA25 A2 TIMG14_C3[2] / UART0_TX[3] / SPI0_PICO[4] / TIMG14_C1[5] / TIMA_FAL2[6] 20 18 16 - - Standard
27 PA26 A1 TIMG8_C0[2] / UART0_RX[3] / SPI0_POCI[4] / BEEP[5] / TIMG14_C0[6] / TIMA_FAL0[7] 1 19 1 - - Standard
28 PA27 A0 TIMG8_C1[2] / SPI0_CS3[3] / TIMA0_C0N[4] / UART0_TX[5] / SPI0_POCI[6] / TIMA_FAL2[7] 2 20 - 1 1 Standard
29 PA28 A5 TIMA0_C0[2] / UART0_RX[3] / TIMG8_IDX[4] 3 1 2 - - Standard
(1) PINCM.PF and PINCM.PC in IOMUX must be set to 0 for analog functions like ADC inputs. Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) that lets users configure the desired Pin Function using the PINCM.PF control bits.
Table 6-2 Digital IO Features by IO Type
IO Structure INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR
Standard-drive Y Y Y
5V tolerant open-drain Y Y Y