SLASEW9C February 2023 – October 2023 MSPM0G1505 , MSPM0G1506 , MSPM0G1507
PRODUCTION DATA
The direct memory access (DMA) controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode, without having to awaken to move data to or from a peripheral.
The DMA in these devices support the following key features:
Table 8-2 lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control bits in the DMA memory mapped registers.
Trigger 0:12 | Source | Trigger 13:24 | Source |
---|---|---|---|
0 | Software | 13 | SPI1 Publisher 1 |
1 | Generic Subscriber 0 (FSUB_0) | 14 | SPI1 Publisher 2 |
2 | Generic Subscriber 1 (FSUB_1) | 15 | UART3 Publisher 1 |
3 |
AES Publisher 1 |
16 | UART3 Publisher 2 |
4 |
AES Publisher 2 |
17 | UART0 Publisher 1 |
5 |
AES Publisher 3 |
18 | UART0 Publisher 2 |
6 |
DAC0 Publisher 2 |
19 | UART1 Publisher 1 |
7 | I2C0 Publisher 1 | 20 | UART1 Publisher 2 |
8 | I2C0 Publisher 2 | 21 | UART2 Publisher 1 |
9 | I2C1 Publisher 1 | 22 | UART2 Publisher 2 |
10 | I2C1 Publisher 2 | 23 | ADC0 Publisher 2 |
11 | SPI0 Publisher 1 | 24 | ADC1 Publisher 2 |
12 | SPI0 Publisher 2 |