SLASFA2
November 2024
MSPM0G1519
,
MSPM0G3519
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Functional Block Diagram
5
Device Comparison
5.1
Device Comparison Chart
6
Pin Configuration and Functions
6.1
Pin Diagrams
6.2
Pin Attributes
11
6.3
Signal Descriptions
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
6.4
Connections for Unused Pins
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Supply Current Characteristics
7.5.1
RUN/SLEEP Modes
7.5.2
STOP/STANDBY Modes
7.5.3
SHUTDOWN Mode
7.6
Power Supply Sequencing
7.6.1
Power Supply Ramp
7.6.2
POR and BOR
7.7
Flash Memory Characteristics
7.8
Timing Characteristics
7.9
Clock Specifications
7.9.1
System Oscillator (SYSOSC)
7.9.2
SYSOSC Typical Frequency Accuracy
7.9.3
Low Frequency Oscillator (LFOSC)
7.9.4
System Phase Lock Loop (SYSPLL)
7.9.5
Low Frequency Crystal/Clock
7.9.6
High Frequency Crystal/Clock
7.10
Digital IO
7.10.1
Electrical Characteristics
7.10.2
Switching Characteristics
7.11
Analog Mux VBOOST
7.12
ADC
7.12.1
Electrical Characteristics
7.12.2
Switching Characteristics
7.12.3
Linearity Parameters
7.12.4
Typical Connection Diagram
7.13
Temperature Sensor
7.14
VREF
7.14.1
Voltage Characteristics
7.14.2
Electrical Characteristics
7.15
Comparator (COMP)
7.15.1
Comparator Electrical Characteristics
7.16
DAC
7.16.1
DAC_Supply Specifications
7.16.2
DAC Output Specifications
7.16.3
DAC Dynamic Specifications
7.16.4
DAC Linearity Specifications
7.16.5
DAC Timing Specifications
7.17
I2C
7.17.1
I2C Characteristics
7.17.2
I2C Filter
7.17.3
I2C Timing Diagram
7.18
SPI
7.18.1
SPI
7.18.2
SPI Timing Diagram
7.19
UART
7.20
TIMx
7.21
TRNG
7.21.1
TRNG Electrical Characteristics
7.21.2
TRNG Switching Characteristics
7.22
Emulation and Debug
7.22.1
SWD Timing
8
Detailed Description
8.1
Functional Block Diagram
8.2
CPU
8.3
Operating Modes
8.3.1
Functionality by Operating Mode (MSPM0Gx51x)
8.4
Security
8.5
Power Management Unit (PMU)
8.6
Clock Module (CKM)
8.7
DMA
8.8
Events
8.9
Memory
8.9.1
Memory Organization
8.9.2
Peripheral File Map
8.9.3
Peripheral Interrupt Vector
8.10
Flash Memory
8.11
SRAM
8.12
GPIO
8.13
IOMUX
8.14
ADC
8.15
Temperature Sensor
8.16
VREF
8.17
COMP
8.18
DAC
8.19
TRNG
8.20
AESADV
8.21
Keystore
8.22
CRC-P
8.23
MATHACL
8.24
UART
8.25
I2C
8.26
SPI
8.27
CAN-FD
8.28
Low-Frequency Sub System (LFSS)
8.29
RTC_B
8.30
IWDT_B
8.31
WWDT
8.32
Timers (TIMx)
8.33
Device Analog Connections
8.34
Input/Output Diagrams
8.35
Serial Wire Debug Interface
8.36
Boot Strap Loader (BSL)
8.37
Device Factory Constants
8.38
Identification
9
Applications, Implementation, and Layout
9.1
Typical Application
9.1.1
Schematic
10
Device and Documentation Support
10.1
Getting Started and Next Steps
10.2
Device Nomenclature
10.3
Tools and Software
10.4
Documentation Support
10.5
Support Resources
10.6
Trademarks
10.7
Electrostatic Discharge Caution
10.8
Glossary
11
Mechanical, Packaging, and Orderable Information
12
Revision History
Package Options
Mechanical Data (Package|Pins)
RGZ|48
MPQF123F
RHB|32
MPQF130D
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slasfa2_oa
Table 6-16 System Controller (SYSCTL) Signal Descriptions
SIGNAL
NAME
PIN
TYPE
DESCRIPTION
RHB PIN
RGZ PIN
PT PIN
PM PIN
PN PIN
PZ PIN
NRST
I
Active-low reset signal (must be logic high for the device to start)
3
4
4
38
6
6