SLASFA2 November 2024 MSPM0G1519 , MSPM0G3519
ADVANCE INFORMATION
MSPM0 MCUs include a low power, high performance SRAM memory with zero wait state access across the supported CPU frequency range of the device. MSPM0 MCUs also provides up to 128KB SRAM. SRAM memory may be used for storing volatile information such as the call stack, heap, global data, and code.
The SRAM memory content is split into two banks of 64kB each. SRAM (Bank 0) provides 64kB of ECC or parity protected SRAM and is always available in run, sleep, stop, and standby operating modes. SRAM (Bank 1) provides 64kB which does not include ECC protection or parity and can be selectively enabled or disabled through BANKOFF1 bit in SRAMCFG register in SYSCTL. When enabled, SRAM (Bank 1) is available in run, sleep, and stop modes. SRAM (Bank 1) can be powered off in STOP mode by configuring the BANKSTOP1 bit in SRAMCFG register in SYSCTL. SRAM contents for both banks are lost in shutdown mode.
A write protection mechanism is provided to allow the application to prevent unintended modifications to the SRAM memory. Write protection is useful when placing executable code into SRAM as it provides a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower power consumption.
Please note that if the DMA controller is to be configured for DMA transfers which access the SRAM, the ECC protected SRAM address region must not be used by the DMA or the CPU. In cases where the DMA must access SRAM, configure the DMA and CPU to use only the parity checked SRAM address region or the unchecked SRAM address region.