SLASF12C February   2023  – October 2023 MSPM0G3105 , MSPM0G3106 , MSPM0G3107

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 GPAMP
      1. 7.15.1 Electrical Characteristics
      2. 7.15.2 Switching Characteristics
    16. 7.16 I2C
      1. 7.16.1 I2C Timing Diagram
      2. 7.16.2 I2C Characteristics
      3. 7.16.3 I2C Filter
    17. 7.17 SPI
      1. 7.17.1 SPI
      2. 7.17.2 SPI Timing Diagram
    18. 7.18 UART
    19. 7.19 TIMx
    20. 7.20 TRNG
      1. 7.20.1 TRNG Electrical Characteristics
      2. 7.20.2 TRNG Switching Characteristics
    21. 7.21 Emulation and Debug
      1. 7.21.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G310x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 TRNG
    17. 8.17 AES
    18. 8.18 CRC
    19. 8.19 UART
    20. 8.20 I2C
    21. 8.21 SPI
    22. 8.22 CAN-FD
    23. 8.23 WWDT
    24. 8.24 RTC
    25. 8.25 Timers (TIMx)
    26. 8.26 Device Analog Connections
    27. 8.27 Input/Output Diagrams
    28. 8.28 Serial Wire Debug Interface
    29. 8.29 Bootstrap Loader (BSL)
    30. 8.30 Device Factory Constants
    31. 8.31 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|28
  • RHB|32
  • DGS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9.3 System Phase Lock Loop (SYSPLL)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSYSPLLREF SYSPLL reference frequency range 4 48 MHz
fVCO VCO output frequency 80 400 MHz
fSYSPLL SYSPLL output frequency range (1) SYSPLLCLK0, SYSPLLCLK1 1 200 MHz
SYSPLLCLK2X 4 800
DCPLL SYSPLL output duty cycle fSYSPLLREF=32MHz, fVCO=160MHz 45 55 %
JitterSYSPLL SYSPLL RMS cycle-to-cycle jitter fSYSPLLREF=32MHz, fVCO=160MHz 24 ps
SYSPLL RMS period jitter 15.5
ISYSPLL SYSPLL current consumption fSYSPLLREF=32MHz, fVCO=160MHz 316 µA
tstart,  SYSPLL SYSPLL start-up time fSYSPLLREF=32MHz, fVCO=160MHz, ±0.5% accuracy 7 18 us
(1) The SYSPLL may support higher output frequencies than the device clock system supports.  Ensure that the device maximum frequency specifications are not violated when configuring the SYSPLL output frequencies.