SLASF12C February   2023  – October 2023 MSPM0G3105 , MSPM0G3106 , MSPM0G3107

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 GPAMP
      1. 7.15.1 Electrical Characteristics
      2. 7.15.2 Switching Characteristics
    16. 7.16 I2C
      1. 7.16.1 I2C Timing Diagram
      2. 7.16.2 I2C Characteristics
      3. 7.16.3 I2C Filter
    17. 7.17 SPI
      1. 7.17.1 SPI
      2. 7.17.2 SPI Timing Diagram
    18. 7.18 UART
    19. 7.19 TIMx
    20. 7.20 TRNG
      1. 7.20.1 TRNG Electrical Characteristics
      2. 7.20.2 TRNG Switching Characteristics
    21. 7.21 Emulation and Debug
      1. 7.21.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G310x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 TRNG
    17. 8.17 AES
    18. 8.18 CRC
    19. 8.19 UART
    20. 8.20 I2C
    21. 8.21 SPI
    22. 8.22 CAN-FD
    23. 8.23 WWDT
    24. 8.24 RTC
    25. 8.25 Timers (TIMx)
    26. 8.26 Device Analog Connections
    27. 8.27 Input/Output Diagrams
    28. 8.28 Serial Wire Debug Interface
    29. 8.29 Bootstrap Loader (BSL)
    30. 8.30 Device Factory Constants
    31. 8.31 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|28
  • RHB|32
  • DGS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9.1 System Oscillator (SYSOSC)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSYSOSC Factory trimmed SYSOSC frequency SYSOSCCFG.FREQ=00 (BASE) 32 MHz
SYSOSCCFG.FREQ=01 4
User trimmed SYSOSC frequency SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=10 24
SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=01 16
fSYSOSC SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed (1) (2) SETUSEFCL=1, Ta = 25 ℃ -0.41 0.58 %
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 85 ℃ -0.80 0.93
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 105 ℃ -0.80 1.09
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 125 ℃ -0.80 1.30
fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies(1) SETUSEFCL=1, Ta = 25 ℃, ±0.1% ±25ppm ROSC -0.5 0.7 %
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 85 ℃, ±0.1% ±25ppm ROSC -1.1 1.2
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 105 ℃, ±0.1% ±25ppm ROSC -1.1 1.4
SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 125 ℃, ±0.1% ±25ppm ROSC -1.1 1.7
fSYSOSC SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled when the internal ROSC resistor is used (4) SETUSEFCL=1 -40 ℃ ≤ Ta ≤ 125 ℃ -1.4 1.8 %
fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHz SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40 ℃ ≤ Ta ≤ 125 ℃ -2.6 1.8 %
fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHz SETUSEFCL=0, SYSOSCCFG.FREQ=01, -40 ℃ ≤ Ta ≤ 125 ℃ -2.7 2.3
fSYSOSC External resistor put between ROSC pin and VSS (1) SETUSEFCL=1 100 kΩ
fSYSOSC Settling time to target accuracy (3) SETUSEFCL=1, ±0.1% 25ppm ROSC  (1) 30 us
fSYSOSC fSYSOSC additional undershoot accuracy during tsettle (3) SETUSEFCL=1, ±0.1% 25ppm ROSC  (1) -11 %
(1) The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an external reference resistor (ROSC) which must be connected between the device ROSC pin and VSS when using the FCL.  Accuracies are shown for a ±0.1% ±25ppm ROSC; relaxed tolerance resistors may also be used (with reduced SYSOSC accuracy).  See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy for various ROSC accuracies.  ROSC does not need to be populated if the FCL is not enabled.
(2) Represents the device accuracy only.  The tolerance and temperature drift of the ROSC resistor used must be combined with this spec to determine final accuracy.  Performance for a ±0.1% ±25ppm ROSC is given as a reference point.
(3) When SYSOSC is waking up (for example, when exiting a low power mode) and FCL is enabled, the SYSOSC will initially undershoot the target frequency fSYSOSC by an additional error of up to fsettle,SYSOSC for the time tsettle,SYSOSC, after which the target accuracy is achieved.
(4) The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an internal reference resistor when using the FCL. See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy.