SLASEX6B February   2023  – October 2023 MSPM0G3505 , MSPM0G3506 , MSPM0G3507

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 Comparator (COMP)
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 DAC
      1. 7.16.1 DAC_Supply Specifications
      2. 7.16.2 DAC Output Specifications
      3. 7.16.3 DAC Dynamic Specifications
      4. 7.16.4 DAC Linearity Specifications
      5. 7.16.5 DAC Timing Specifications
    17. 7.17 GPAMP
      1. 7.17.1 Electrical Characteristics
      2. 7.17.2 Switching Characteristics
    18. 7.18 OPA
      1. 7.18.1 Electrical Characteristics
      2. 7.18.2 Switching Characteristics
      3. 7.18.3 PGA Mode
    19. 7.19 I2C
      1. 7.19.1 I2C Characteristics
      2. 7.19.2 I2C Filter
      3. 7.19.3 I2C Timing Diagram
    20. 7.20 SPI
      1. 7.20.1 SPI
      2. 7.20.2 SPI Timing Diagram
    21. 7.21 UART
    22. 7.22 TIMx
    23. 7.23 TRNG
      1. 7.23.1 TRNG Electrical Characteristics
      2. 7.23.2 TRNG Switching Characteristics
    24. 7.24 Emulation and Debug
      1. 7.24.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G350x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 COMP
    16. 8.16 DAC
    17. 8.17 OPA
    18. 8.18 GPAMP
    19. 8.19 TRNG
    20. 8.20 AES
    21. 8.21 CRC
    22. 8.22 MATHACL
    23. 8.23 UART
    24. 8.24 I2C
    25. 8.25 SPI
    26. 8.26 CAN-FD
    27. 8.27 WWDT
    28. 8.28 RTC
    29. 8.29 Timers (TIMx)
    30. 8.30 Device Analog Connections
    31. 8.31 Input/Output Diagrams
    32. 8.32 Serial Wire Debug Interface
    33. 8.33 Bootstrap Loader (BSL)
    34. 8.34 Device Factory Constants
    35. 8.35 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.1 Schematic

TI recommends connecting a combination of a 10-µF and a 0.1-µF low-ESR ceramic decoupling capacitor across the VDD and VSS pins, as well as placing these capacitors as close as possible to the supply pins that they decouple (within a few millimeters) to achieve a minimal loop area. The 10-µF bulk decoupling capacitor is a recommended value for most applications, but this capacitance can be adjusted if needed based upon the PCB design and application requirements. For example, larger bulk capacitors can be used, but this can affect the supply rail ramp-up time.

The NRST reset pin must be pulled up to VDD (supply level) for the device to release from RESET state and start the boot process. TI recommends connecting an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor for most applications, enabling the NRST pin to be controlled by another device or a debug probe.

The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ with 0.1% tolerance resistor with a temperature coefficient (TCR) of 25ppm/C or better populated between the ROSC pin and VSS. This resistor establishes a reference current to stabilize the SYSOSC frequency through a correction loop. This resistor is required if the FCL feature is used for higher accuracy, and it is not required if the SYSOSC FCL is not enabled. When the FCL mode is not used, the PA2 pin can be used as a digital input/output pin.

A 0.47-µF tank capacitor is required for the VCORE pin and must be placed close to the device with minimum distance to the device ground. Do not connect other circuits to the VCORE pin.

For the 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high for I2C and UART functions, as the open drain IO only implement a low-side NMOS driver and no high-side PMOS driver. The 5-V-tolerant open drain IOs are fail-safe and can have a voltage present even if VDD is not supplied.


GUID-20230427-SS0I-F6CD-WV9M-7KFHRGHKBNW0-low.svg

Figure 9-1 Basic Application Schematic