The CPU sub system (MCPUSS) implements an ARM
Cortex-M0+ CPU, an instruction pre-fetch/cache, a system timer, a
memory protection unit, and interrupt management features. The ARM
Cortex-M0+ is a cost-optimized, 32-bit CPU which delivers high
performance and low power to embedded applications. Key features of
the CPU Sub System include:
- ARM
Cortex-M0+ CPU supporting clock frequencies from
32kHz to 80MHz
- ARMv6-M Thumb instruction set (little endian)
with single-cycle 32x32 multiply instruction
- Single-cycle access to GPIO registers via ARM
single-cycle IO port
- Pre-fetch
logic to improve sequential code execution, and
I-cache with 4 64-bit cache lines
- System
timer (SysTick) with 24-bit down counter and
automatic reload
- Memory
protection unit (MPU) with 8 programmable
regions
- Nested
vectored interrupt controller (NVIC) with 4
programmable priority levels and tail-chaining
- Interrupt
groups for expanding the total interrupt sources,
with jump index for low interrupt latency