SLASFA2 November   2024 MSPM0G3519

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Chart
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
      15.      27
      16.      28
      17.      29
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
        1. 7.9.2.1 SYSOSC Typical Frequency Accuracy
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 Comparator (COMP)
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 DAC
      1. 7.16.1 DAC_Supply Specifications
      2. 7.16.2 DAC Output Specifications
      3. 7.16.3 DAC Dynamic Specifications
      4. 7.16.4 DAC Linearity Specifications
      5. 7.16.5 DAC Timing Specifications
    17. 7.17 I2C
      1. 7.17.1 I2C Characteristics
      2. 7.17.2 I2C Filter
      3. 7.17.3 I2C Timing Diagram
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0Gx51x)
    4. 8.4  Security
    5. 8.5  Power Management Unit (PMU)
    6. 8.6  Clock Module (CKM)
    7. 8.7  DMA
    8. 8.8  Events
    9. 8.9  Memory
      1. 8.9.1 Memory Organization
      2. 8.9.2 Peripheral File Map
      3. 8.9.3 Peripheral Interrupt Vector
    10. 8.10 Flash Memory
    11. 8.11 SRAM
    12. 8.12 GPIO
    13. 8.13 IOMUX
    14. 8.14 ADC
    15. 8.15 Temperature Sensor
    16. 8.16 Low-Frequency Sub System (LFSS)
    17. 8.17 VREF
    18. 8.18 COMP
    19. 8.19 DAC
    20. 8.20 TRNG
    21. 8.21 AESADV
    22. 8.22 Keystore
    23. 8.23 CRC-P
    24. 8.24 MATHACL
    25. 8.25 UART
    26. 8.26 I2C
    27. 8.27 SPI
    28. 8.28 CAN-FD
    29. 8.29 IWDT_B
    30. 8.30 WWDT
    31. 8.31 RTC_B
    32. 8.32 Timers (TIMx)
    33. 8.33 Device Analog Connections
    34. 8.34 Input/Output Diagrams
    35. 8.35 Serial Wire Debug Interface
    36. 8.36 Boot Strap Loader (BSL)
    37. 8.37 Device Factory Constants
    38. 8.38 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Core
    • Arm® 32-bit Cortex® M0+ CPU with memory protection unit, frequency up to 80MHz
  • Functional Safety-Compliant targeted

    • Developed for functional safety applications

    • Functional Safety Manual and FMEDA available to aid in functional safety system design

    • Systematic capability up to ASIL B targeted

  • Operating characteristics
    • Extended temperature: –40°C up to 125°C
    • Wide supply voltage range: 1.62V to 3.6V
  • Memories
    • Up to 512KB of flash memory with error correction code (ECC)

      • Dual-bank with address swap for OTA updates

    • 16KB data flash bank with ECC protection
    • 128KB total SRAM
      • SRAM (Bank 0): 64kB SRAM with ECC protection or hardware parity, and retention down to STANDBY mode
      • SRAM (Bank 1) : 64kB SRAM with retention down to SLEEP mode
  • High-performance analog peripherals
    • Two simultaneous sampling 12-bit 4Msps analog-to-digital converters (ADCs) with up to 27 external channels
      • 14-bit effective resolution at 250ksps with hardware averaging
    • One 12-bit 1-MSPS digital-to-analog converter with integrated output buffer (DAC)
    • Three high-speed comparators (COMP) with integrated 8-bit reference DACs
      • 32ns propagation delay in high-speed mode
      • Support low-power mode operation down to <1µA
    • Programmable analog connections between ADC, COMP and DAC
    • Configurable 1.4V or 2.5V internal shared voltage reference (VREF)
    • Integrated temperature sensor
  • Optimized low-power modes
    • RUN: 121µA/MHz (CoreMark)
    • SLEEP: 614µA at 4MHz
    • STOP: 56µA at 32 kHz
    • STANDBY: 1.7µA with RTC and SRAM retention
    • SHUTDOWN: 93nA with IO wake-up capability
  • Intelligent digital peripherals
    • 12-channel DMA controller
    • Math accelerator supports DIV, SQRT, MAC and TRIG computations
    • Nine timers support up to 28 PWM channels
      • Three 16-bit general-purpose timers
      • Two 16-bit general-purpose timers support QEI
      • One 16-bit general-purpose timer support low-power operation in STANDBY mode
      • One 32-bit high-resolution general-purpose timer
      • Two 16-bit advanced timers with deadband support and complimentary outputs up to 12 PWM channels
    • Two windowed watchdog timers (WWDT), one independent watchdog timer (IWDT)
    • RTC with alarm and calendar mode
  • Enhanced communication interfaces
    • Seven UART interfaces
      • Two supporting LIN, IrDA, DALI, Smart Card, Manchester
      • Five basic instances, including one supporting low-power operation in STANDBY mode
    • Three I2C interfaces supporting up to FM+ (1Mbit/s), SMBus/PMBus, and wakeup from STOP mode
    • Three SPIs supports up to 32Mbits/s
    • Two Controller Area Network (CAN) interfaces support CAN 2.0 A or B and CAN-FD
  • Clock system
    • Internal 4 to 32MHz oscillator with up to ±1.2% accuracy (SYSOSC)
    • Phase-locked loop (PLL) up to 80MHz
    • Internal 32kHz low-frequency oscillator (LFOSC) with ±3% accuracy
    • External 4 to 48MHz crystal oscillator (HFXT)
    • External 32kHz crystal oscillator(LFXT)
    • External clock input
  • Data integrity and encryption
    • AES-128/256 accelerator with support for GCM/GMAC, CCM/CBC-MAC, CBC, CTR
    • Secure Key Storage for up to four AES keys
    • Flexible firewalls for protecting code and data
    • True random number generator (TRNG)
    • Cyclic redundancy checker (CRC-16, CRC-32)
    • Extensive security features
  • Flexible I/O features
    • Up to 94 GPIOs
      • Two 5V-tolerant open-drain IOs
      • Three high-drive IOs with 20mA drive strength

      • Four high-speed IOs

  • Development support
    • 2-pin serial wire debug (SWD)
  • Package options
    • 100-pin LQFP (0.5mm pitch)

    • 80-pin LQFP (0.5mm pitch)

    • 64-pin LQFP (0.5mm pitch)

    • 48-pin LQFP (0.5mm pitch)

    • 48-pin VQFN (0.5mm pitch)

    • 32-pin VQFN (0.5mm pitch)

  • Family members (also see Device Comparison)
    • MSPM0G3519: 512KB flash, 128KB RAM
    • MSPM0G3518: 256KB flash, 128KB RAM
    • MSPM0G1519: 512KB flash, 128KB RAM
    • MSPM0G1518: 256KB flash, 128KB RAM
  • Development kits and software (also see Tools and Software)