SLASFA2 November   2024 MSPM0G3519

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Chart
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
      15.      27
      16.      28
      17.      29
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
        1. 7.9.2.1 SYSOSC Typical Frequency Accuracy
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 Comparator (COMP)
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 DAC
      1. 7.16.1 DAC_Supply Specifications
      2. 7.16.2 DAC Output Specifications
      3. 7.16.3 DAC Dynamic Specifications
      4. 7.16.4 DAC Linearity Specifications
      5. 7.16.5 DAC Timing Specifications
    17. 7.17 I2C
      1. 7.17.1 I2C Characteristics
      2. 7.17.2 I2C Filter
      3. 7.17.3 I2C Timing Diagram
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0Gx51x)
    4. 8.4  Security
    5. 8.5  Power Management Unit (PMU)
    6. 8.6  Clock Module (CKM)
    7. 8.7  DMA
    8. 8.8  Events
    9. 8.9  Memory
      1. 8.9.1 Memory Organization
      2. 8.9.2 Peripheral File Map
      3. 8.9.3 Peripheral Interrupt Vector
    10. 8.10 Flash Memory
    11. 8.11 SRAM
    12. 8.12 GPIO
    13. 8.13 IOMUX
    14. 8.14 ADC
    15. 8.15 Temperature Sensor
    16. 8.16 Low-Frequency Sub System (LFSS)
    17. 8.17 VREF
    18. 8.18 COMP
    19. 8.19 DAC
    20. 8.20 TRNG
    21. 8.21 AESADV
    22. 8.22 Keystore
    23. 8.23 CRC-P
    24. 8.24 MATHACL
    25. 8.25 UART
    26. 8.26 I2C
    27. 8.27 SPI
    28. 8.28 CAN-FD
    29. 8.29 IWDT_B
    30. 8.30 WWDT
    31. 8.31 RTC_B
    32. 8.32 Timers (TIMx)
    33. 8.33 Device Analog Connections
    34. 8.34 Input/Output Diagrams
    35. 8.35 Serial Wire Debug Interface
    36. 8.36 Boot Strap Loader (BSL)
    37. 8.37 Device Factory Constants
    38. 8.38 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

8.32 Timers (TIMx)

There are two timer peripherals in these devices support that following key features: TIMGx (general-purpose timer) and TIMAx (advanced timer). TIMGx is a subset of TIMAx, which means common features between timer instances are software compatible. For specific configurations, see Table 8-14:

Specific features for the general-purpose timer (TIMGx) include:

  • 16-/32-bit up, down, up-down or down-up counter, with repeat-reload mode
  • Selectable and configurable clock source
  • 8-bit programmable prescaler to divide the counter clock frequency
  • Two independent channels for
    • Output compare
    • Input capture
    • PWM output
    • One-shot mode
  • Shadow CC register available in TIMG6, TIMG7 and TIMG12
  • Shadow register for load available in TIMG6, TIMG7
  • Support quadrature encoder interface (QEI) and Hall sensor input logic available in TIMG8, TIMG9
  • Support synchronization and cross trigger among different TIMx instances in the same power domain
  • Support interrupt/DMA trigger generation and cross peripherals (such as ADC) trigger capability

Specific features for the advanced timer (TIMAx) include:

  • 16-bit down or up-down counter, with repeat-reload mode
  • Selectable and configurable clock source
  • 8-bit programmable prescaler to divide the counter clock frequency
  • Repeat counter to generate an interrupt or event only after a given number of cycles of the counter
  • Up to four independent channels for
    • Output compare
    • Input capture
    • PWM output
    • One-shot mode
  • Shadow register for load and CC register available in both TIMA0 and TIMA1
  • Complementary output PWM with programmable dead band insertion
  • Asymmetric PWM
  • Configurable fault handling mechanism for
    • Fast PWM responses (<40ns) to external fault inputs or comparator events
    • Outputting signals in a safe user-defined state when a latched fault condition has occurred
  • Support synchronization and cross trigger among different TIMx instances in the same power domain
  • Support interrupt and DMA trigger generation and cross peripherals (such as ADC) trigger capability
  • Two additional capture/compare channels for internal events
Table 8-14 TIMx Configurations
TIMER NAME POWER DOMAIN RESOLUTION PRESCALER REPEAT COUNTER CAPTURE / COMPARE CHANNELS PHASE LOAD SHADOW LOAD SHADOW CC DEADBAND FAULT QEI
TIMG0 PD0 16 bit 8 bit – 2 – – – – – –
TIMG6 PD1 16 bit 8 bit – 2 – – – – – –
TIMG7 PD1 16 bit 8 bit – 2 – Yes Yes – – –
TIMG8 PD0 16 bit 8 bit – 2 – – – – – Yes
TIMG9 PD0 16 bit 8 bit – 2 – – – – – Yes
TIMG12 PD1 32bit – – 2 – – Yes – – –
TIMG14 PD0 16 bit 8 bit – 4 – – – – – –
TIMA0 PD1 16 bit 8 bit 8 bit 4 Yes Yes Yes Yes Yes –
TIMA1 PD1 16 bit 8 bit 8 bit 2 Yes Yes Yes Yes Yes –

For more details, see the TIMx chapter of the MSPM0 G-Series 80MHz Microcontrollers Technical Reference Manual.