SLASFA2 Data sheet

SLASFA2 November 2024 MSPM0G3519

ADVANCE INFORMATION

Package Options

Mechanical Data (Package|Pins)

PN|80
- MTQF010B
PZ|100
- MTQF013A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

slasfa2_oa

7.8 Timing Characteristics

VDD=3.3V, T_a=25℃ (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	UNIT
Wakeup Timing
t_{WAKE, SLEEP1}	Wakeup time from SLEEP1 to RUN ⁽¹⁾		1.6	us
t_{WAKE, SLEEP2}	Wakeup time from SLEEP2 to RUN ⁽¹⁾		2.2	us
t_{WAKE, STANDBY0}	Wakeup time from STANDBY0 to RUN ⁽¹⁾		10.4	us
t_{WAKE, STANDBY1}	Wakeup time from STANDBY1 to RUN ⁽¹⁾		10.4	us
t_{WAKE, STOP0}	Wakeup time from STOP0 to RUN (SYSOSC enabled) ⁽¹⁾		7.6	us
t_{WAKE, STOP1}	Wakeup time from STOP1 to RUN (SYSOSC enabled) ⁽¹⁾		9.6	us
t_{WAKE, STOP2}	Wakeup time from STOP2 to RUN (SYSOSC disabled) ⁽¹⁾		8.4	us
t_{WAKEUP, SHDN}	Wakeup time from SHUTDOWN to RUN ⁽²⁾	Fast boot enabled	306	us
t_{WAKEUP, SHDN}	Wakeup time from SHUTDOWN to RUN ⁽²⁾	Fast boot disabled	314	us
Asynchronous Fast Clock Request Timing
t_{DELAY, SLEEP1}	Delay time from edge of asynchronous request to first 32MHz MCLK edge	Mode is SLEEP1	0.34	us
t_{DELAY, SLEEP2}	Delay time from edge of asynchronous request to first 32MHz MCLK edge	Mode is SLEEP2	0.94	us
t_{DELAY, STANDBY0}	Delay time from edge of asynchronous request to first 32MHz MCLK edge	Mode is STANDBY0	3	us
t_{DELAY, STANDBY1}	Delay time from edge of asynchronous request to first 32MHz MCLK edge	Mode is STANDBY1	3.1	us
t_{DELAY, STOP0}	Delay time from edge of asynchronous request to first 32MHz MCLK edge	Mode is STOP0	0.1	us
t_{DELAY, STOP1}	Delay time from edge of asynchronous request to first 32MHz MCLK edge	Mode is STOP1	2.4	us
t_{DELAY, STOP2}	Delay time from edge of asynchronous request to first 32MHz MCLK edge	Mode is STOP2	0.9	us
Startup Timing
t_{START, RESET}	Device cold startup time from reset/power-up ⁽³⁾	Fast boot enabled	300	us
t_{START, RESET}	Device cold startup time from reset/power-up ⁽³⁾	Fast boot disabled	350	us
NRST Timing
t_{RST, BOOTRST}	Pulse length on NRST pin to generate BOOTRST	ULPCLK≥4MHz	1.5	us
t_{RST, BOOTRST}	Pulse length on NRST pin to generate BOOTRST	ULPCLK=32kHz	29	us
t_{RST, POR}	Pulse length on NRST pin to generate POR		1	s

(1) The wake-up time is measured from the edge of an external wake-up signal (GPIO wake-up event) to the time that the first instruction of the user program is executed, with glitch filter disabled (FILTEREN=0x0) and fast wake enabled (FASTWAKEONLY=1) .

(2) The wake-up time is measured from the edge of an external wake-up signal (IOMUX wake-up event) to the time that first instruction of the user program is executed.

(3) The start-up time is measured from the time that VDD crosses VBOR0- (cold start-up) to the time that the first instruction of the user program is executed.