SLASEX5C October   2022  – January 2024 MSPM0L1105 , MSPM0L1106

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 GPAMP
      1. 7.15.1 Electrical Characteristics
      2. 7.15.2 Switching Characteristics
    16. 7.16 I2C
      1. 7.16.1 I2C Characteristics
      2. 7.16.2 I2C Filter
      3. 7.16.3 I2C Timing Diagram
    17. 7.17 SPI
      1. 7.17.1 SPI
      2. 7.17.2 SPI Timing Diagram
    18. 7.18 UART
    19. 7.19 TIMx
    20. 7.20 Emulation and Debug
      1. 7.20.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0L110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 SPI
    19. 8.19 I2C
    20. 8.20 WWDT
    21. 8.21 Timers (TIMx)
    22. 8.22 Device Analog Connections
    23. 8.23 Input/Output Diagrams
    24. 8.24 Bootstrap Loader (BSL)
    25. 8.25 Serial Wire Debug Interface
    26. 8.26 Device Factory Constants
    27. 8.27 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|28
  • DYY|16
  • RGE|24
  • RHB|32
  • RTR|16
  • DGS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.7.1 Memory Organization

Table 8-4 summarizes the memory map of the devices. For more information about the memory region detail, see the Platform Memory Map section in the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual.

Table 8-4 Memory Organization
Memory RegionSubregionMSPM0L1105MSPM0L1106
Code (Flash)MAIN (3)

32KB - 8B(1)

0x0000.0000 to 0x0000.7FF8

64KB - 8B(1)

0x0000.0000 to 0x0000.FFF8
Aliased MAIN (2)(3)0x0040.0000 to 0x0040.7FF80x0040.0000 to 0x0040.FFF8
SRAM (SRAM)SRAM

4KB

0x2000.0000 to 0x2000.1000

4KB

0x2000.0000 to 0x2000.1000
Aliased SRAM(2)0x2000.0000 to 0x2000.10000x2000.0000 to 0x2000.1000
PeripheralPeripherals0x4000.0000 to 0x40FF.FFFF0x4000.0000 to 0x40FF.FFFF
MAIN (3)0x0000.0000 to 0x0000.7FF80x0000.0000 to 0x0000.FFF8
Aliased MAIN(2)(3)0x0040.0000 to 0x0040.7FF80x0040.0000 to 0x0040.FFF8
NONMAIN

512 bytes

0x41C0.0000 to 0x41C0.0200

512 bytes

0x41C0.0000 to 0x41C0.0200
Aliased NONMAIN (2)0x41C1.0000 to 0x41C1.02000x41C1.0000 to 0x41C1.0200
FACTORY 0x41C4.0000 to 0x41C4.00800x41C4.0000 to 0x41C4.0080
Aliased FACTORY (2)0x41C5.0000 to 0x41C5.00800x41C5.0000 to 0x41C5.0080
Subsystem0x6000.0000 to 0x7FFF.FFFF0x6000.0000 to 0x7FFF.FFFF
System PPB0xE000.0000 to 0xE00F.FFFF0xE000.0000 to 0xE00F.FFFF
(1) First 32KB flash memory (address 0x0000.0000 to 0x0000.8000) has up to 100000 program and erase cycles.
(2) Aliased memory reads the same as the corresponding memory region. Aliased memory is included to keep the compatibility with devices that have ECC.
(3) CPU access to one of the last 8 bytes of a flash region will cause a hard fault. This occurs because the prefetch logic tries to read one flash word (64 bits) ahead, resulting in a read attempt to an invalid memory location.