SLASEX5C October   2022  – January 2024 MSPM0L1105 , MSPM0L1106

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 GPAMP
      1. 7.15.1 Electrical Characteristics
      2. 7.15.2 Switching Characteristics
    16. 7.16 I2C
      1. 7.16.1 I2C Characteristics
      2. 7.16.2 I2C Filter
      3. 7.16.3 I2C Timing Diagram
    17. 7.17 SPI
      1. 7.17.1 SPI
      2. 7.17.2 SPI Timing Diagram
    18. 7.18 UART
    19. 7.19 TIMx
    20. 7.20 Emulation and Debug
      1. 7.20.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0L110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 SPI
    19. 8.19 I2C
    20. 8.20 WWDT
    21. 8.21 Timers (TIMx)
    22. 8.22 Device Analog Connections
    23. 8.23 Input/Output Diagrams
    24. 8.24 Bootstrap Loader (BSL)
    25. 8.25 Serial Wire Debug Interface
    26. 8.26 Device Factory Constants
    27. 8.27 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|28
  • DYY|16
  • RGE|24
  • RHB|32
  • RTR|16
  • DGS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Pin Attributes

Table 6-1 describes the functions available on every pin for each device package.

Note: Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) that lets users configure the desired Pin Function using the PINCM.PF control bits.
Table 6-1 Pin Attributes
PINCMx PIN FUNCTION PIN NUMBER I/O Structure

PIN NAME

 ANALOG DIGITAL (1) 32 VQFN 28 VSSOP 24 VQFN 20 VSSOP 16 WQFN 16 SOT
N/A VDD 4 7 3 6 6 5 Power
N/A VSS 5 8 4 7 7 6 Power
N/A VCORE 32 3 23 3 3 2 Power
1 PA0 UART1_TX [2] / I2C0_SDA [3] / TIMG1_C0 [4] / SPI0_CS1 [5](Default BSL I2C_SDA) 1 4 24 4 4 3 5-V Tolerant Open-Drain
2 PA1 UART1_RX [2] / I2C0_SCL [3] / TIMG1_C1 [4](Default BSL I2C_SCL) 2 5 1 5 5 4 5-V Tolerant Open-Drain
N/A NRST 3 6 2 Reset(2)
3 PA2 ROSC TIMG1_C1 [2] / SPI0_CS0 [3] 6 9 5 8 8 7 Standard
4 PA3 TIMG2_C0 [2] / SPI0_CS1 [3] / UART1_CTS [4] 7 10 6 – – – Standard
5 PA4 TIMG2_C1 [2] / SPI0_POCI [3] / UART1_RTS [4] 8 11 7 9 – – Standard
6 PA5 TIMG0_C0 [2] / SPI0_PICO [3]/FCC_IN[4] 9 12 – – 9 – High-Speed
7 PA6 TIMG0_C1 [2] / SPI0_SCK [3] 10 13 – 10 10 8 Standard
8 PA7 CLK_OUT [3] / TIMG1_C0 [4] 11 – – – – – Standard
9 PA8 UART0_TX [2] / SPI0_CS0 [3] / UART1_RTS [4] / TIMG2_C0 [5] 12 – – – – – Standard
10 PA9 UART0_RX [2] / SPI0_PICO [3] / UART1_CTS [4] / TIMG2_C1 [5] 13 14 8 – – – Standard
11 PA10 UART1_TX [2] / SPI0_POCI [3] / I2C0_SDA [4] / TIMG4_C0 [5] 14 15 9 – 11 – High-Speed
12 PA11 UART1_RX [2] / SPI0_SCK [3] / I2C0_SCL [4] / TIMG4_C1 [5] 15 16 10 11 – – Standard
13 PA12 UART0_CTS [2] / TIMG0_C0 [3]/FCC_IN[4] 16 – – – – – Standard
14 PA13 UART0_RTS [2] / TIMG0_C1 [3] / UART1_RX [4] 17 – – – – – Standard
15 PA14 UART1_CTS [2] / CLK_OUT [3] / UART1_TX [4] / TIMG1_C0 [5] 18 17 – – – – Standard
16 PA15 A9 UART1_RTS [2] / SPI0_CS2 [4] / TIMG4_C1 [5] 19 18 11 – 12 – Standard
17 PA16 A8 SPI0_POCI [4] / TIMG0_C0 [5]/FCC_IN[6] 20 19 12 12 13 – Standard
18 PA17 UART0_TX [2] / SPI0_SCK [4] / TIMG4_C0 [5] / SPI0_CS1 [6] 21 20 13 13 – 9 Standard with wake
19 PA18 A7 / GPAMP_IN- UART0_RX [2] / SPI0_PICO [3] / TIMG4_C1 [5] (BSL Invoke) 22 21 14 14 14 10 Standard with wake
20 PA19 SWDIO [2] / SPI0_POCI [4] 23 22 15 15 15 11 High-Speed
21 PA20 A6 SWCLK [2] / TIMG4_C0 [4] 24 23 16 16 16 12 Standard
22 PA21 A5 / VREF- TIMG2_C0 [2] / UART0_CTS [3] / UART0_TX [4] 25 24 17 – – – Standard
23 PA22 A4 / GPAMP_OUT UART0_RX [2] / TIMG2_C1 [3] / UART0_RTS [4] / CLK_OUT [5] / UART1_RX [6](Default BSL UART_RX) 26 25 18 17 1 13 Standard
24 PA23 VREF+ UART0_TX [2] / SPI0_CS3 [3] / TIMG0_C0 [4] / UART0_CTS [5] / UART1_TX [6](Default BSL UART_TX) 27 26 19 18 2 14 Standard
25 PA24 A3 SPI0_CS2 [2] / TIMG0_C1 [3] / UART0_RTS [4] 28 27 20 19 – 15 Standard
26 PA25 A2 TIMG4_C1 [2] / UART0_TX [3] / SPI0_PICO [4] 29 28 21 20 2 16 Standard
27 PA26 A1 / GPAMP_IN+ TIMG1_C0 [2] / UART0_RX [3] / SPI0_POCI [4] 30 1 22 1 – 1 Standard
28 PA27 A0 TIMG1_C1 [2] / SPI0_CS3 [3] 31 2 – 2 – – Standard
(1) PINCM.PF and PINCM.PC in IOMUX must be set to 0 for analog functions (for example, GPAMP inputs and outputs or ADC inputs). Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) that lets users configure the desired Pin Function using the PINCM.PF control bits.
(2) Reset PIN is muxed with PA1 for 16-pin and 20-pin devices.
Table 6-2 Digital IO Features by IO Type
IO Structure INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC
Standard-drive Y Y Y
Standard-drive with wake Y Y Y Y
High-speed Y Y Y Y
5-V tolerant open-drain Y Y Y Y