SLASEX5C October   2022  – January 2024 MSPM0L1105 , MSPM0L1106

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 GPAMP
      1. 7.15.1 Electrical Characteristics
      2. 7.15.2 Switching Characteristics
    16. 7.16 I2C
      1. 7.16.1 I2C Characteristics
      2. 7.16.2 I2C Filter
      3. 7.16.3 I2C Timing Diagram
    17. 7.17 SPI
      1. 7.17.1 SPI
      2. 7.17.2 SPI Timing Diagram
    18. 7.18 UART
    19. 7.19 TIMx
    20. 7.20 Emulation and Debug
      1. 7.20.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0L110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 SPI
    19. 8.19 I2C
    20. 8.20 WWDT
    21. 8.21 Timers (TIMx)
    22. 8.22 Device Analog Connections
    23. 8.23 Input/Output Diagrams
    24. 8.24 Bootstrap Loader (BSL)
    25. 8.25 Serial Wire Debug Interface
    26. 8.26 Device Factory Constants
    27. 8.27 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|28
  • DYY|16
  • RGE|24
  • RHB|32
  • RTR|16
  • DGS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.15.1 Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCM Common mode voltage range RRI = 0x0 -0.1 VDD–1 V
RRI = 0x1 1 VDD-0.2
RRI = 0x2 -0.1 VDD-0.2
Iq Quiescent current, per op-amp IO= 0 mA, RRI = 0x0 97 µA
IO= 0 mA, RRI = 0x1 or 0x2 93
GBW Gain-bandwidth product CL = 200pF 0.32 MHz
VOS Input offset voltage Noninverting, unity gain, TA = 25℃, VDD = 3.3V CHOPCLKMODE = 0x0 ±0.2 ±6.5 mV
CHOPCLKMODE = 0x1 ±0.08 ±0.4
dVOS/dT Input offset voltage temperature drift Noninverting, unity gain CHOPCLKMODE = 0x0 7.7 µV/°C
CHOPCLKMODE = 0x1 0.34
Ibias Input bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x0 TA = 25°C ±40 pA
TA = 125°C ±4000
0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x1 TA = 25°C ±200
TA = 125°C ±4000
CMRRDC Common mode rejection ratio, DC Over common mode voltage range CHOPCLKMODE = 0x0 48 77 dB
CHOPCLKMODE = 0x1 56 105
en Input voltage noise density Noninverting, unity gain f = 1 kHz 43 nV/√Hz
f = 10 kHz 19
Rin Input resistance (1) 0.65 kΩ
Cin Input capacitance Common mode 4 pF
Differential 2
AOL Open-loop voltage gain, DC RL = 350 kΩ, 0.3 < Vo < VDD-0.3 82 90 107 dB
PM phase margin CL = 200 pF, RL= 350 kΩ 69 70 72 degree
SR Slew rate Noninverting, unity gain, CL = 40 pF 0.32 V/µs
THDN Total Harmonic Distortion + Noise 0.012 %
ILoad Output load current ±4 mA
CLoad Output load capacitance 200 pF
(1) The term 'Rin' refers to the input resistance of the multiplexer (mux) in the GPAMP.