SLASFC9 December   2024 MSPM0L1117

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Table
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 Low Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 I2C
      1. 7.15.1 I2C Characteristics
      2. 7.15.2 I2C Filter
      3. 7.15.3 I2C Timing Diagram
    16. 7.16 SPI
      1. 7.16.1 SPI
      2. 7.16.2 SPI Timing Diagram
    17. 7.17 UART
    18. 7.18 TIMx
    19. 7.19 TRNG Electrical Characteristics
    20. 7.20 TRNG Switching Characteristics
    21. 7.21 Emulation and Debug
      1. 7.21.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode
    4. 8.4  Security
    5. 8.5  Power Management Unit (PMU)
    6. 8.6  Clock Module (CKM)
    7. 8.7  DMA
    8. 8.8  Events
    9. 8.9  Memory
      1. 8.9.1 Memory Organization
      2. 8.9.2 Peripheral File Map
      3. 8.9.3 Peripheral Interrupt Vector
    10. 8.10 Flash Memory
    11. 8.11 SRAM
    12. 8.12 GPIO
    13. 8.13 IOMUX
    14. 8.14 ADC
    15. 8.15 Temperature Sensor
    16. 8.16 VREF
    17. 8.17 TRNG
    18. 8.18 AESADV
    19. 8.19 Keystore
    20. 8.20 CRC-P
    21. 8.21 UART
    22. 8.22 I2C
    23. 8.23 SPI
    24. 8.24 Low-Frequency Sub System (LFSS)
    25. 8.25 RTC_B
    26. 8.26 IWDT_B
    27. 8.27 WWDT
    28. 8.28 Timers (TIMx)
    29. 8.29 Device Analog Connections
    30. 8.30 Input/Output Diagrams
    31. 8.31 Serial Wire Debug Interface
    32. 8.32 Bootstrap Loader (BSL)
    33. 8.33 Device Factory Constants
    34. 8.34 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8 Timing Characteristics

VDD=3.3V, Ta=25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Wakeup Timing
tWAKE, SLEEP0 Wakeup time from SLEEP0 to RUN (1) 1.2 us
tWAKE, SLEEP1 Wakeup time from SLEEP1 to RUN (1) 1.5 us
tWAKE, SLEEP2 Wakeup time from SLEEP2 to RUN (1) 2.1 us
tWAKE, STANDBY0 Wakeup time from STANDBY0 to RUN (1) 9.9 us
tWAKE, STANDBY1 Wakeup time from STANDBY1 to RUN (1) 9.9 us
tWAKE, STOP0 Wakeup time from STOP0 to RUN (SYSOSC enabled) (1) 7 us
tWAKE, STOP1 Wakeup time from STOP1 to RUN (SYSOSC enabled) (1) 8.8 us
Wakeup time from STOP2 to RUN (SYSOSC disabled) (1) 7.8
tWAKEUP, SHDN Wakeup time from SHUTDOWN to RUN (2) Fast boot enabled 270 us
Fast boot disabled 290
Asynchronous Fast Clock Request Timing
tDELAY, SLEEP1 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP1 0.35 us
tDELAY, SLEEP2 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP2 0.92 us
tDELAY, STANDBY0 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STANDBY0 3.1 us
tDELAY, STANDBY1 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STANDBY1 3.1 us
tDELAY, STOP0 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STOP0 0.1 us
tDELAY, STOP1 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STOP1 2.2 us
tDELAY, STOP2 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STOP2 0.9 us
Startup Timing
tSTART, RESET Device cold startup time from reset/power-up (3) Fast boot enabled 300 us
Fast boot disabled 310
NRST Timing
tRST, BOOTRST Pulse length on NRST pin to generate BOOTRST ULPCLK≥4MHz 1.5 us
ULPCLK=32kHz 80
tRST, POR Pulse length on NRST pin to generate POR 1 s
(1) The wake-up time is measured from the edge of an external wake-up signal (GPIO wake-up event) to the time that the first instruction of the user program is executed, with glitch filter disabled (FILTEREN=0x0) and fast wake enabled (FASTWAKEONLY=1) .
(2) The wake-up time is measured from the edge of an external wake-up signal (IOMUX wake-up event) to the time that first instruction of the user program is executed.
(3) The start-up time is measured from the time that VDD crosses VBOR0- (cold start-up) to the time that the first instruction of the user program is executed.