SLASFB5
May 2024
MSPM0L1228-Q1
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Functional Block Diagram
5
Device Comparison
5.1
Device Comparison Chart
6
Pin Configuration and Functions
6.1
Pin Diagrams
6.2
Pin Attributes
11
6.3
Signal Descriptions
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
6.4
Connections for Unused Pins
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Supply Current Characteristics
7.5.1
RUN/SLEEP Modes
7.5.2
STOP/STANDBY Modes
7.5.3
SHUTDOWN Mode
7.6
Power Supply Sequencing
7.6.1
Power Supply Ramp
7.6.2
POR and BOR
7.7
VBat Characteristics
7.8
Flash Memory Characteristics
7.9
Timing Characteristics
7.10
Clock Specifications
7.10.1
System Oscillator (SYSOSC)
7.10.2
Low Frequency Oscillator (LFOSC)
7.10.3
High Frequency Crystal/Clock
7.10.4
Low Frequency Crystal/Clock
7.11
Digital IO
7.11.1
Electrical Characteristics
7.11.2
Switching Characteristics
7.12
Analog Mux VBOOST
7.13
ADC
7.13.1
Electrical Characteristics
7.13.2
Switching Characteristics
7.13.3
Linearity Parameters
7.13.4
Typical Connection Diagram
7.14
Temperature Sensor
7.15
VREF
7.15.1
Electrical Characteristics ADC
7.15.2
Electrical Characteristics (Comparator)
7.15.3
Voltage Characteristics (ADC)
7.15.4
Voltage Characteristics (Comparator)
7.16
Comparator (COMP)
7.16.1
Comparator Electrical Characteristics
7.17
LCD
7.18
I2C
7.18.1
I2C Characteristics
7.18.2
I2C Filter
7.18.3
I2C Timing Diagram
7.19
SPI
7.19.1
SPI
7.19.2
SPI Timing Diagram
7.20
UART
7.21
TIMx
7.22
TRNG
7.22.1
TRNG Electrical Characteristics
7.22.2
TRNG Switching Characteristics
7.23
Emulation and Debug
7.23.1
SWD Timing
8
Detailed Description
8.1
CPU
8.2
Operating Modes
8.2.1
Functionality by Operating Mode (MSPM0Lx22x)
8.3
Security
8.4
Power Management Unit (PMU)
8.5
Clock Module (CKM)
8.6
DMA
8.7
Events
8.8
Memory
8.8.1
Memory Organization
8.8.2
Peripheral File Map
8.8.3
Peripheral Interrupt Vector
8.9
Flash Memory
8.10
SRAM
8.11
GPIO
8.12
IOMUX
8.13
ADC
8.14
Temperature Sensor
8.15
LFSS
8.16
VREF
8.17
COMP
8.18
TRNG
8.19
AESADV
8.20
Keystore
8.21
CRC
8.22
UART
8.23
I2C
8.24
SPI
8.25
IWDT
8.26
WWDT
8.27
RTC_A
8.28
Timers (TIMx)
8.29
LCD
8.30
Device Analog Connections
8.31
Input/Output Diagrams
8.32
Serial Wire Debug Interface
8.33
Bootstrap Loader (BSL)
8.34
Device Factory Constants
8.35
Identification
9
Applications, Implementation, and Layout
9.1
Typical Application
9.1.1
Schematic
10
Device and Documentation Support
10.1
Getting Started and Next Steps
10.2
Device Nomenclature
10.3
Tools and Software
10.4
Documentation Support
10.5
Support Resources
10.6
Trademarks
10.7
Electrostatic Discharge Caution
10.8
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGE|24
MPQF124G
RHB|32
MPQF130D
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slasfb5_oa
1
Features
AEC-Q100 Grade 1 qualified for automotive applications
Core
Arm®
32-bit
Cortex®
-M0+ CPU with memory protection unit, frequency up to 32MHz
PSA-L1 Certified
Operating characteristics
Extended temperature: –40°C up to 125°C
Wide supply voltage range: 1.62V to 3.6V
Memories
Up to 256KB of flash memory with ECC
Dual-bank with address swap with OTA updates
32KB of SRAM with ECC or parity
32B backup memory
(1)
High-performance analog peripherals
12-bit 1.68Msps analog-to-digital converter (ADC), up to 26 external channels
Configurable 1.4V or 2.5V internal shared voltage reference (VREF)
Comparator (COMP) with 8-bit reference DAC
Integrated temperature sensor
User interface
Ultra-low power segmented LCD controller supporting up to 8×51 and 4×55 LCD displays
(2)
Optimized low-power modes
RUN:105µA/MHz (CoreMark)
STOP: 60µA at 32kHz
STANDBY 1.2µA (VDD), 1.1µA (VBAT) with 32kHz, LFXT, RTC, and SRAM and registers fully retained
SHUTDOWN: 80nA (VDD), 1.1µA (VBAT) with 32kHz, LFXT, RTC, and I/O wake-up
Intelligent digital peripherals
7-channel DMA controller
15-channel event fabric signaling system
Six timers supporting up to 18 PWM outputs, all operational down to STANDBY mode
One 16-bit advanced timer with deadband
One 32-bit general-purpose timer
Four 16-bit general-purpose timers
Window-watchdog timer (WWDT)
Independent watchdog timer (IWDT) residing in the VBAT island
Communication interfaces
Five UART modules, with two supporting LIN, IrDA, DALI, smart card, Manchester
Three I
2
C modules supporting SMBus/PMBus and wakeup from STOP mode, with two supporting up to FM+ (1Mbps)
Two SPI modules supporting up to 16Mbps
Clock system
Internal 4MHz to 32MHz oscillator with up to ±1.2% accuracy (SYSOSC)
Internal 32kHz oscillator (LFOSC) with ±3% accuracy
1
External 4MHz to 32MHz crystal oscillator (HFXT)
External 32kHz crystal oscillator (LFXT)
1
External LF
1
and HF digital clock inputs
Digital clock output
Data integrity and encryption
AES accelerator with support for GCM/GMAC, CCM/CBC-MAC, CBC, CTR
Secure Key Storage for up to four AES keys
Flexible firewalls for protecting code and data
True random number generator (TRNG)
Cyclic redundancy checker (CRC-16, CRC-32)
VBAT island (auxiliary supply)
1
Independent supply with dedicated VBAT pin
Real-time clock (RTC)
Tamper detection with timestamp
Independent watchdog timer (IWDT)
Scratch Pad Memory (SPM)
Flexible I/O features
Up to 73 total GPIOs
Up to 5 GPIOs supplied by VBAT pin
1
Support for FuSa
ISO26262 ASIL B
Development support
2-pin serial wire debug (SWD)
Package options
80-pin LQFP (0.5mm and 0.4mm pitch options)
64-pin LQFP (0.5mm and 0.4mm pitch options)
48-pin LQFP, VQFN
(3)
32-pin VQFN
3
24-pin VQFN
3
Family members
(also see
Device Comparison
)
MSPM0L2228: 256KB flash, LCD
MSPM0L2227: 128KB flash, LCD
MSPM0L1228: 256KB flash
MSPM0L1227: 128KB flash
Development kits and software
(also see
Tools and Software
)
LP-MSPM0L2228
LaunchPad™
development kit
MSP Software Development Kit (SDK)
1.
Part of the LFSS (Low Frequency Subsystem) supplied by the VBAT pin residing in the VBAT island
2.
MSPM0L222x devices only
3.
VQFN packages have wettable flanks.