SLASFB5 May   2024 MSPM0L1228-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Chart
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
      15.      27
      16.      28
      17.      29
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  VBat Characteristics
    8. 7.8  Flash Memory Characteristics
    9. 7.9  Timing Characteristics
    10. 7.10 Clock Specifications
      1. 7.10.1 System Oscillator (SYSOSC)
      2. 7.10.2 Low Frequency Oscillator (LFOSC)
      3. 7.10.3 High Frequency Crystal/Clock
      4. 7.10.4 Low Frequency Crystal/Clock
    11. 7.11 Digital IO
      1. 7.11.1 Electrical Characteristics
      2. 7.11.2 Switching Characteristics
    12. 7.12 Analog Mux VBOOST
    13. 7.13 ADC
      1. 7.13.1 Electrical Characteristics
      2. 7.13.2 Switching Characteristics
      3. 7.13.3 Linearity Parameters
      4. 7.13.4 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Electrical Characteristics ADC
      2. 7.15.2 Electrical Characteristics (Comparator)
      3. 7.15.3 Voltage Characteristics (ADC)
      4. 7.15.4 Voltage Characteristics (Comparator)
    16. 7.16 Comparator (COMP)
      1. 7.16.1 Comparator Electrical Characteristics
    17. 7.17 LCD
    18. 7.18 I2C
      1. 7.18.1 I2C Characteristics
      2. 7.18.2 I2C Filter
      3. 7.18.3 I2C Timing Diagram
    19. 7.19 SPI
      1. 7.19.1 SPI
      2. 7.19.2 SPI Timing Diagram
    20. 7.20 UART
    21. 7.21 TIMx
    22. 7.22 TRNG
      1. 7.22.1 TRNG Electrical Characteristics
      2. 7.22.2 TRNG Switching Characteristics
    23. 7.23 Emulation and Debug
      1. 7.23.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0Lx22x)
    3. 8.3  Security
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 LFSS
    16. 8.16 VREF
    17. 8.17 COMP
    18. 8.18 TRNG
    19. 8.19 AESADV
    20. 8.20 Keystore
    21. 8.21 CRC
    22. 8.22 UART
    23. 8.23 I2C
    24. 8.24 SPI
    25. 8.25 IWDT
    26. 8.26 WWDT
    27. 8.27 RTC_A
    28. 8.28 Timers (TIMx)
    29. 8.29 LCD
    30. 8.30 Device Analog Connections
    31. 8.31 Input/Output Diagrams
    32. 8.32 Serial Wire Debug Interface
    33. 8.33 Bootstrap Loader (BSL)
    34. 8.34 Device Factory Constants
    35. 8.35 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

8.2.1 Functionality by Operating Mode (MSPM0Lx22x)

Supported functionality in each operating mode is given in Table 8-1.

Functional key:

  • EN: The function is enabled in the specified mode.
  • DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained.
  • OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled.
  • NS: The function is not automatically disabled in the specified mode but is not supported.
  • OFF: The function is fully powered off in the specified mode, and no configuration information is retained. When waking up from an OFF state, all module registers must be re-configured to the desired settings by application software.
Table 8-1 Supported Functionality by Operating Mode
OPERATING MODE RUN SLEEP STOP STANDBY SHUTDOWN
RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1
Oscillators SYSOSC EN EN DIS EN EN DIS OPT(1) EN DIS DIS DIS OFF
LFOSC or LFXT EN (LFOSC or LFXT) OFF
HFXT OPT DIS DIS OPT DIS DIS DIS DIS DIS DIS DIS OFF
Clocks CPUCLK 32MHz 32kHz 32kHz DIS OFF
MCLK to PD1 32MHz 32kHz 32kHz 32MHz 32kHz 32kHz DIS OFF
ULPCLK to PD0 32MHz 32kHz 32kHz 32MHz 32kHz 32kHz 4MHz(1) 4MHz 32kHz DIS OFF
ULPCLK to TIMG0, TIMG4, TIMG5, TIMG8, TIMG12, TIMA0 32MHz 32kHz 32kHz 32MHz 32kHz 32kHz 4MHz(1) 4MHz 32kHz OFF
RTCCLK 32kHz OFF
MFCLK OPT DIS OPT DIS OPT DIS OFF
MFPCLK OPT DIS OPT DIS OPT DIS OFF
LFCLK 32kHz DIS OFF
LFCLK to TIMG0, TIMG4, TIMG5, TIMG8, TIMG12, TIMA0 32kHz OFF
LFCLK Monitor OPT OFF
MCLK Monitor OPT DIS OFF
PMU POR monitor EN
BOR monitor EN OFF
Core regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF
Core Functions CPU EN DIS OFF
DMA OPT DIS (triggers supported) OFF
Flash EN DIS OFF
SRAM EN DIS OFF
PD1 Peripherals CRC OPT OFF
SPI0, SPI1 OPT

OFF
AESADV OPT OFF
PD0 Peripherals Keystore OPT OFF
UART0, UART1, UART2, UART3, UART4 OPT OPT(2) OFF
I2C0, I2C1 OPT OPT(2) OFF
TIMG0, TIMG4, TIMG5, TIMG8, TIMG12 OPT OFF
TIMA0 OPT OFF
COMP0 OPT OFF
LCD OPT OFF
GPIOA, GPIOB, GPIOC(3) OPT OPT(2) OFF
WWDT0 OPT DIS OFF
LFSS Peripherals IWDT OPT OPT
RTC_A OPT OPT
Tamper I/O, SPM OPT OPT
Analog TRNG OPT OFF
ADC0 (3) OPT NS (triggers supported) OFF
COMP0 OPT OPT (ULP) OPT OPT (ULP) OPT OPT (ULP) OFF
IOMUX and IO Wakeup EN DIS w/ WAKE
Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST, SWD
(1) If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as in RUN1, and ULPCLK remains at 32kHz as in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as in RUN2, and ULPCLK remains at 32kHz as in RUN2.
(2) When using the STANDBY1 policy for STANDBY, all TIMx instances and the RTC are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked.
(3) For ADCx and GPIO Ports A, B and C, the digital logic is in PD0 and the register interface is in PD1. These peripherals support fast single-cycle register access when PD1 is active and also support basic operation down to STANDBY mode where PD0 is still active.