SLASEX0 Data sheet

PRODUCTION DATA

Refer to the PDF data sheet for device specific package drawings

over operating free-air temperature range (unless otherwise noted)

PARAMETERS		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SPI
f_SPI	SPI clock frequency	Clock max speed = 32MHz 1.62 < VDD < 3.6V Controller mode			16	MHz
f_SPI	SPI clock frequency	Clock max speed = 32MHz 1.62 < VDD < 3.6V Peripheral mode			16	MHz
DC_SCK	SCK Duty Cycle		40	50	60	%
Controller
t_{SCLK_H/L}	SCLK High or Low time		(tSPI/2) - 1	tSPI / 2	(tSPI/2) + 1	ns
t_SU.CI	POCI input data setup time ⁽¹⁾	2.7 < VDD < 3.6V, delayed sampling enabled	1			ns
t_SU.CI	POCI input data setup time ⁽¹⁾	1.62 < VDD < 2.7V, delayed sampling enabled	1			ns
t_SU.CI	POCI input data setup time ⁽¹⁾	2.7 < VDD < 3.6V, no delayed sampling	27			ns
t_SU.CI	POCI input data setup time ⁽¹⁾	1.62 < VDD < 2.7V, no delayed sampling	35			ns
t_HD.CI	POCI input data hold time		9			ns
t_VALID.CO	PICO output data valid time ⁽²⁾				10	ns
t_HD.CO	PICO output data hold time ⁽³⁾		1			ns
Peripheral
t_CS.LEAD	CS lead-time, CS active to clock		8			ns
t_CS.LAG	CS lag time, Last clock to CS inactive		1			ns
t_CS.ACC	CS access time, CS active to POCI data out				23	ns
t_CS.DIS	CS disable time, CS inactive to POCI high impedance				19	ns
t_SU.PI	PICO input data setup time		7			ns
t_HD.PI	PICO input data hold time		31.25			ns
t_VALID.PO	POCI output data valid time⁽²⁾	2.7 < VDD < 3.6V			24	ns
t_VALID.PO	POCI output data valid time⁽²⁾	1.62 < VDD < 2.7V			31	ns
t_HD.PO	POCI output data hold time⁽³⁾		5			ns

(1) The POCI input data setup time can be fully compensated when delayed sampling feature is enabled.

(2) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge

(3) Specifies how long data on the output is valid after the output changing SCLK clock edge