SLASEX0D October   2022  – January 2024 MSPM0L1303 , MSPM0L1304 , MSPM0L1305 , MSPM0L1306 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 COMP
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 GPAMP
      1. 7.16.1 Electrical Characteristics
      2. 7.16.2 Switching Characteristics
    17. 7.17 OPA
      1. 7.17.1 Electrical Characteristics
      2. 7.17.2 Switching Characteristics
      3. 7.17.3 PGA Mode
    18. 7.18 I2C
      1. 7.18.1 I2C Characteristics
      2. 7.18.2 I2C Filter
      3. 7.18.3 I2C Timing Diagram
    19. 7.19 SPI
      1. 7.19.1 SPI
      2. 7.19.2 SPI Timing Diagram
    20. 7.20 UART
    21. 7.21 TIMx
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 COMP
    16. 8.16 CRC
    17. 8.17 GPAMP
    18. 8.18 OPA
    19. 8.19 I2C
    20. 8.20 SPI
    21. 8.21 UART
    22. 8.22 WWDT
    23. 8.23 Timers (TIMx)
    24. 8.24 Device Analog Connections
    25. 8.25 Input/Output Diagrams
    26. 8.26 Serial Wire Debug Interface
    27. 8.27 Bootstrap Loader (BSL)
    28. 8.28 Device Factory Constants
    29. 8.29 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Pin Attributes

The following table describes the functions available on every pin for each device package.

Note: Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits.
Table 6-1 Pin Attributes
PINCMxPIN NAMEPIN FUNCTIONPIN NUMBERI/O STRUCTURE
ANALOGDIGITAL(1)32 VQFN28 VSSOP (2)28 VSSOP (3)24 VQFN20 VSSOP16 WQFN16 SOT
N/AN/AVDD4773665Power
N/AN/AVSS5884776Power
N/AN/AVCORE323323332Power
1PA0UART1_TX [2] / I2C0_SDA [3] / TIMG1_C0 [4] / SPI0_CS1 [5](Default BSL I2C_SDA)144244435-V tolerant Open-Drain
2PA1UART1_RX [2] / I2C0_SCL [3] / TIMG1_C1 [4](Default BSL I2C_SCL)25515545-V tolerant Open-Drain
N/AN/ANRST3662Reset(4)
3PA2ROSCTIMG1_C1 [2] / SPI0_CS0 [3]6995887Standard
4PA3TIMG2_C0 [2] / SPI0_CS1 [3] / UART1_CTS [4] / COMP0_OUT [5]710106–––Standard
5PA4 TIMG2_C1 [2] / SPI0_POCI [3] / UART1_RTS [4]8111179––Standard
6PA5 TIMG0_C0 [2] / SPI0_PICO [3]/FCC_IN[4]91212––9–High-Speed
7PA6 TIMG0_C1 [2] / SPI0_SCK [3]101313–10108Standard
8PA7 COMP0_OUT [2] / CLK_OUT [3] / TIMG1_C0 [4]11––––––Standard
9PA8 UART0_TX [2] / SPI0_CS0 [3] / UART1_RTS [4] / TIMG2_C0 [5]12––––––Standard
10PA9 UART0_RX [2] / SPI0_PICO [3] / UART1_CTS [4] / TIMG2_C1 [5]/CLK_OUT[6]1314148–––Standard
11PA10 UART1_TX [2] / SPI0_POCI [3] / I2C0_SDA [4] / TIMG4_C0 [5]/CLK_OUT[6]1415159–11–High-Speed
12PA11 UART1_RX [2] / SPI0_SCK [3] / I2C0_SCL [4] / TIMG4_C1 [5] / COMP0_OUT [6]1516161011––Standard
13PA12 UART0_CTS [2] / TIMG0_C0 [3]/FCC_IN[4]16––––––Standard
14PA13 UART0_RTS [2] / TIMG0_C1 [3] / UART1_RX [4]17–-––––Standard
15PA14 UART1_CTS [2] / CLK_OUT [3] / UART1_TX [4] / TIMG1_C0 [5]181717––––Standard
16PA15A9 UART1_RTS [2] / I2C1_SCL [3] / SPI0_CS2 [4] / TIMG4_C1 [5]19181811–12–Standard
17PA16A8 / OPA1_OUT COMP0_OUT [2] / I2C1_SDA [3] / SPI0_POCI [4] / TIMG0_C0 [5]/FCC_IN[6]201919121213–Standard
18PA17OPA1_IN1- UART0_TX [2] / I2C1_SCL [3] / SPI0_SCK [4] / TIMG4_C0 [5] / SPI0_CS1 [6]2120-1313 (2)–9Standard with wake
N/AOPA1_IN0-
N/AN/AOPA1_IN0-––20–13 (3)14–Analog
19PA18A7 / OPA1_IN0+ / GPAMP_IN-UART0_RX [2] / SPI0_PICO [3] / I2C1_SDA [4] / TIMG4_C1 [5](BSL Invoke)222121141410Standard with wake
20PA19 SWDIO [2] / I2C1_SDA [3] / SPI0_POCI [4]23222215151511High-Speed
21PA20A6 / COMP0_IN1+ SWCLK [2] / I2C1_SCL [3] / TIMG4_C0 [4]24232316161612Standard
22PA21A5 / VREF- TIMG2_C0 [2] / UART0_CTS [3] / UART0_TX [4]25242417–––Standard
23PA22A4 / GPAMP_OUT / OPA0_OUTUART0_RX [2] / TIMG2_C1 [3] / UART0_RTS [4] / CLK_OUT [5] / UART1_RX [6](Default BSL UART_RX)2625251817113Standard
24PA23VREF+ / COMP0_IN1-UART0_TX [2] / SPI0_CS3 [3] / TIMG0_C0 [4] / UART0_CTS [5] / UART1_TX [6](Default BSL UART_TX)2726261918214Standard
25PA24A3 / OPA0_IN1- / OPA0_IN0- SPI0_CS2 [2] / TIMG0_C1 [3] / UART0_RTS [4]2827–2019(2)–15Standard
N/AN/AOPA0_IN0-––27–19(3)––Analog
26PA25A2 / OPA0_IN0+ TIMG4_C1 [2] / UART0_TX [3] / SPI0_PICO [4]2928282120216Standard
27PA26A1 / GPAMP_IN+ / COMP0_IN0+ TIMG1_C0 [2] / UART0_RX [3] / SPI0_POCI [4]3011221–1Standard
28PA27A0 / COMP0_IN0- TIMG1_C1 [2] / SPI0_CS3 [3]3122–2––Standard
(1) PINCM.PF and PINCM.PC in IOMUX must be set to 0 for analog functions (for example, OPA inputs or outputs or COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which lets software configure the desired Pin Function using the PINCM.PF control bits.
(2) MSPM0L130x only
(3) MSPM0L134x only
(4) Reset PIN is muxed with PA1 for 16-pin and 20-pin devices.
Table 6-2 Digital IO Features by IO Type
IO STRUCTUREINVERSION CONTROLDRIVE STRENGTH CONTROLHYSTERESIS CONTROLPULLUP RESISTORPULLDOWN RESISTORWAKEUP LOGIC
Standard driveYYY
Standard drive with wakeYYYY
High speedYYYY
5-V tolerant open drainYYYY