SLASFB5A May   2024  – November 2024 MSPM0L1228-Q1 , MSPM0L2228-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Device Comparison Chart
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
    3. 6.3 Signal Descriptions
      1.      13
      2.      14
      3.      15
      4.      16
      5.      17
      6.      18
      7.      19
      8.      20
      9.      21
      10.      22
      11.      23
      12.      24
      13.      25
      14.      26
      15.      27
      16.      28
      17.      29
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  VBat Characteristics
    8. 7.8  Flash Memory Characteristics
    9. 7.9  Timing Characteristics
    10. 7.10 Clock Specifications
      1. 7.10.1 System Oscillator (SYSOSC)
      2. 7.10.2 Low Frequency Oscillator (LFOSC)
      3. 7.10.3 Low Frequency Crystal/Clock
      4. 7.10.4 High Frequency Crystal/Clock
    11. 7.11 Digital IO
      1. 7.11.1 Electrical Characteristics
      2. 7.11.2 Switching Characteristics
    12. 7.12 Analog Mux VBOOST
    13. 7.13 ADC
      1. 7.13.1 Electrical Characteristics
      2. 7.13.2 Switching Characteristics
      3. 7.13.3 Linearity Parameters
      4. 7.13.4 Typical Connection Diagram
    14. 7.14 Temperature Sensor
    15. 7.15 VREF
      1. 7.15.1 Electrical Characteristics ADC
      2. 7.15.2 Electrical Characteristics (Comparator)
      3. 7.15.3 Voltage Characterisitcs (ADC)
      4. 7.15.4 Voltage Characterisitcs (Comparator)
    16. 7.16 Comparator (COMP)
      1. 7.16.1 Comparator Electrical Characteristics
    17. 7.17 LCD
    18. 7.18 I2C
      1. 7.18.1 I2C Characteristics
      2. 7.18.2 I2C Filter
      3. 7.18.3 I2C Timing Diagram
    19. 7.19 SPI
      1. 7.19.1 SPI
      2. 7.19.2 SPI Timing Diagram
    20. 7.20 UART
    21. 7.21 TIMx
    22. 7.22 TRNG
      1. 7.22.1 TRNG Electrical Characteristics
      2. 7.22.2 TRNG Switching Characteristics
    23. 7.23 Emulation and Debug
      1. 7.23.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0Lx22x)
    4. 8.4  Security
    5. 8.5  Power Management Unit (PMU)
    6. 8.6  Clock Module (CKM)
    7. 8.7  DMA
    8. 8.8  Events
    9. 8.9  Memory
      1. 8.9.1 Memory Organization
      2. 8.9.2 Peripheral File Map
      3. 8.9.3 Peripheral Interrupt Vector
    10. 8.10 Flash Memory
    11. 8.11 SRAM
    12. 8.12 GPIO
    13. 8.13 IOMUX
    14. 8.14 ADC
    15. 8.15 Temperature Sensor
    16. 8.16 LFSS
    17. 8.17 VREF
    18. 8.18 COMP
    19. 8.19 TRNG
    20. 8.20 AESADV
    21. 8.21 Keystore
    22. 8.22 CRC
    23. 8.23 UART
    24. 8.24 I2C
    25. 8.25 SPI
    26. 8.26 IWDT
    27. 8.27 WWDT
    28. 8.28 RTC_A
    29. 8.29 Timers (TIMx)
    30. 8.30 LCD
    31. 8.31 Device Analog Connections
    32. 8.32 Input/Output Diagrams
    33. 8.33 Serial Wire Debug Interface
    34. 8.34 Bootstrap Loader (BSL)
    35. 8.35 Device Factory Constants
    36. 8.36 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PM|64
  • PN|80
  • PT|48
Thermal pad, mechanical data (Package|Pins)

8.29 Timers (TIMx)

There are two timer peripherals in these devices support that following key features: TIMGx (general-purpose timer) and TIMAx (advanced timer). TIMGx is a subset of TIMAx, which means these timers share many common features that are compatible in software. For specific configuration, see Table 8-11:

Specific features for the general-purpose timer (TIMGx) include:

  • 16-bit and 32-bit timers with up, down or up-down counting modes, with repeat-reload mode
  • Selectable and configurable clock source
  • 8-bit programmable prescaler to divide the counter clock frequency
  • Two independent CC channels for
    • Output compare
    • Input capture
    • PWM output
    • One-shot mode
  • Support quadrature encoder interface (QEI) for positioning and movement sensing available in TIMG8
  • Support synchronization and cross trigger among different TIMx instances in the same power domain
  • Support interrupt/DMA trigger generation and cross peripherals (such as ADC) trigger capability
  • Cross trigger event logic for Hall sensor inputs (TIMG8)

Specific features for the advanced timer (TIMAx) include:

  • 16-bit timer with up, down or up-down counting modes, with repeat-reload mode
  • Selectable and configurable clock source
  • 8-bit programmable prescaler to divide the counter clock frequency
  • Repeat counter to generate an interrupt or event only after a given number of cycles of the counter
  • Up to four independent CC channels for
    • Output compare
    • Input capture
    • PWM output
    • One-shot mode
  • Two additional capture/compare channels for internal events (CC4/CC5)
  • Shadow register for load and CC register available in TIMA0
  • Complementary output PWM
  • Asymmetric PWM with programmable dead band insertion
  • Fault handling mechanism to ensure the output signals in a safe user-defined state when a fault condition is encountered
  • Support synchronization and cross trigger among different TIMx instances in the same power domain
  • Support interrupt and DMA trigger generation and cross peripherals (such as ADC) trigger capability
  • Two additional capture/compare channels for internal events
Table 8-11 TIMx Instance Configuration
InstancePower DomainCounter ResolutionPrescalerRepeat CounterCCP Channels (External/Internal)External PWM ChannelsPhase LoadShadow LoadShadow CCsDeadbandFault HandlerQEI / Hall Input Mode
TIMG0PD016-bit8-bit-22------
TIMG4PD016-bit8-bit-22-YesYes---
TIMG5PD016-bit8-bit-22-YesYes---
TIMG8PD016-bit8-bit-22-----Yes
TIMG12PD032-bit--22--Yes---
TIMA0PD016-bit8-bitYes4/28YesYesYesYesYes-
Table 8-12 TIMx Cross Trigger Map (PD0)
TSEL.ETSEL SelectionTIMA0TIMG0TIMG4TIMG5TIMG8TIMG12
0TIMA0.TRIGOTIMA0.TRIGOTIMA0.TRIGOTIMA0.TRIGOTIMA0.TRIGOTIMA0.TRIGO
1TIMG0.TRIGOTIMG0.TRIGOTIMG0.TRIGOTIMG0.TRIGOTIMG0.TRIGOTIMG0.TRIGO
2TIMG4.TRIGOTIMG4.TRIGOTIMG4.TRIGOTIMG4.TRIGOTIMG4.TRIGOTIMG4.TRIGO
3TIMG5.TRIGOTIMG5.TRIGOTIMG5.TRIGOTIMG5.TRIGOTIMG5.TRIGOTIMG5.TRIGO
4TIMG8.TRIGOTIMG8.TRIGOTIMG8.TRIGOTIMG8.TRIGOTIMG8.TRIGOTIMG8.TRIGO
5TIMG12.TRIGOTIMG12.TRIGOTIMG12.TRIGOTIMG12.TRIGOTIMG12.TRIGOTIMG12.TRIGO
6 to 15Reserved
16Event Subscriber Port 0 (FSUB0)
17Event Subscriber Port 1 (FSUB1)
18-31Reserved

The following tests can be applied as functional safety mechanisms for this module (to provide diagnostic coverage on a specific function):

Table 8-13 Timers Safety Mechanisms

Safety Mechanism

Description

Faults/Failure modes

TIM1

Test for PWM generation

Targeted towards PWM generation logic, including the counters, compare registers, clocking logic, output generation logic etc.

TIM2

Periodic Software Read Back of IP Static Configuration Registers

Targets the static configuration registers in Timer.

TIM3(latent fault coverage)

Test for fault generation

This test is a test for diagnostic, which checks the functioning of fault detection logic in timer.

Note:

This test is applicable only to TIMAx.

TIM4

Fault detection to take the PWMs to safe state

This safety mechanism can be used to detect faults which result in system level failures like over/under voltages/currents. The external faults can be monitored using the fault pins or the analog comparators. The faults which can be covered include the faults in the PWM generation logic, faults in external drivers etc.

Note:

This test is applicable only to TIMAx.

TIM5

Input capture on two or more timer instances

This test is used to cover the faults in the capture mode logic. The faults could be in clocking, capture logic, counter logic etc.

TIM6

Timer period monitoring.

This test is a run time check in which the duration between two interrupts can be measured (using another timer). This is useful in detecting faults which result in the counter taking more or less time than expected and can also cover the clocking related faults.

WDT

Windowed watchdog event

Targeted towards faults which result in missing interrupts (periodic interrupts) affecting the program sequence of the CPU. These could be faults in the interrupt logic or the logic which sets the interrupt flags or the logic which generated hardware triggers for other IPs (ADC for example) etc.