The MUX36S16 and MUX36D08 (MUX36xxx) are modern complementary metal-oxide semiconductor (CMOS) precision analog multiplexers (muxes). The MUX36S16 offers 16:1 single-ended channels, whereas the MUX36D08 offers differential 8:1 or dual 8:1 single-ended channels. The MUX36S16 and MUX36D08 work equally well with either dual supplies (±5 V to ±18 V) or a single supply (10 V to 36 V). These devices also perform well with symmetric supplies (such as VDD = 12 V, VSS = –12 V), and unsymmetric supplies (such as VDD = 12 V, VSS = –5 V). All digital inputs have transistor-transistor logic (TTL) compatible thresholds, providing both TTL and CMOS logic compatibility when operating in the valid supply voltage range.
The MUX36S16 and MUX36D08 have very low on- and off-leakage currents, allowing these multiplexers to switch signals from high input impedance sources with minimal error. A low supply current of 45 µA enables use in power-sensitive applications.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
MUX36S16
MUX36D08 |
TSSOP (28) | 9.70 mm × 6.40 mm |
SOIC (28) | 17.9 mm × 7.50 mm | |
WQFN (RTV) (32) | 5.00 mm × 5.00 mm | |
WQFN (RSN) (32) | 4.00 mm × 4.00 mm |
Changes from B Revision (April 2018) to C Revision
Changes from A Revision (November 2017) to B Revision
Changes from * Revision (November 2016) to A Revision
PIN | FUNCTION | DESCRIPTION | ||
---|---|---|---|---|
NAME | TSSOP/ SOIC | WQFN | ||
A0 | 17 | 15 | Digital input | Address line 0 |
A1 | 16 | 14 | Digital input | Address line 1 |
A2 | 15 | 11 | Digital input | Address line 2 |
A3 | 14 | 10 | Digital input | Address line 3 |
D | 28 | 29 | Analog input or output | Drain pin. Can be an input or output. |
EN | 18 | 16 | Digital input | Active high digital input. When this pin is low, all switches are turned off. When this pin is high, the A[3:0] logic inputs determine which switch is turned on. |
GND | 12 | 9 | Power supply | Ground (0 V) reference |
NC | 2, 3, 13 | 12, 13, 26, 27, 28, 30, 32 | No connect | Do not connect |
S1 | 19 | 17 | Analog input or output | Source pin 1. Can be an input or output. |
S2 | 20 | 18 | Analog input or output | Source pin 2. Can be an input or output. |
S3 | 21 | 19 | Analog input or output | Source pin 3. Can be an input or output. |
S4 | 22 | 20 | Analog input or output | Source pin 4. Can be an input or output. |
S5 | 23 | 21 | Analog input or output | Source pin 5. Can be an input or output. |
S6 | 24 | 22 | Analog input or output | Source pin 6. Can be an input or output. |
S7 | 25 | 23 | Analog input or output | Source pin 7. Can be an input or output. |
S8 | 26 | 24 | Analog input or output | Source pin 8. Can be an input or output. |
S9 | 11 | 8 | Analog input or output | Source pin 9. Can be an input or output. |
S10 | 10 | 7 | Analog input or output | Source pin 10. Can be an input or output. |
S11 | 9 | 6 | Analog input or output | Source pin 11. Can be an input or output. |
S12 | 8 | 5 | Analog input or output | Source pin 12. Can be an input or output. |
S13 | 7 | 4 | Analog input or output | Source pin 13. Can be an input or output. |
S14 | 6 | 3 | Analog input or output | Source pin 14. Can be an input or output. |
S15 | 5 | 2 | Analog input or output | Source pin 15. Can be an input or output. |
S16 | 4 | 1 | Analog input or output | Source pin 16. Can be an input or output. |
VDD | 1 | 31 | Power supply | Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. |
VSS | 27 | 25 | Power supply | Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. |
PIN | FUNCTION | DESCRIPTION | ||
---|---|---|---|---|
NAME | TSSOP/ SOIC | WQFN | ||
A0 | 17 | 15 | Digital input | Address line 0 |
A1 | 16 | 14 | Digital input | Address line 1 |
A2 | 15 | 10 | Digital input | Address line 2 |
DA | 28 | 27 | Analog input or output | Drain pin A. Can be an input or output. |
DB | 2 | 31 | Analog input or output | Drain pin B. Can be an input or output. |
EN | 18 | 16 | Digital input | Active high digital input. When this pin is low, all switches are turned off. When this pin is high, the A[2:0] logic inputs determine which pair of switches is turned on. |
GND | 12 | 9 | Power supply | Ground (0 V) reference |
NC | 3, 13, 14 | 11, 12, 13, 26, 28, 30, 32 | No connect | Do not connect |
S1A | 19 | 17 | Analog input or output | Source pin 1A. Can be an input or output. |
S2A | 20 | 18 | Analog input or output | Source pin 2A. Can be an input or output. |
S3A | 21 | 19 | Analog input or output | Source pin 3A. Can be an input or output. |
S4A | 22 | 20 | Analog input or output | Source pin 4A. Can be an input or output. |
S5A | 23 | 21 | Analog input or output | Source pin 5A. Can be an input or output. |
S6A | 24 | 22 | Analog input or output | Source pin 6A. Can be an input or output. |
S7A | 25 | 23 | Analog input or output | Source pin 7A. Can be an input or output. |
S8A | 26 | 24 | Analog input or output | Source pin 8A. Can be an input or output. |
S1B | 11 | 8 | Analog input or output | Source pin 1B. Can be an input or output. |
S2B | 10 | 7 | Analog input or output | Source pin 2B. Can be an input or output. |
S3B | 9 | 6 | Analog input or output | Source pin 3B. Can be an input or output. |
S4B | 8 | 5 | Analog input or output | Source pin 4B. Can be an input or output. |
S5B | 7 | 4 | Analog input or output | Source pin 5B. Can be an input or output. |
S6B | 6 | 3 | Analog input or output | Source pin 6B. Can be an input or output. |
S7B | 5 | 2 | Analog input or output | Source pin 7B. Can be an input or output. |
S8B | 4 | 1 | Analog input or output | Source pin 8B. Can be an input or output. |
VDD | 1 | 29 | Power supply | Positive power supply. This pin is the most positive power supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. |
VSS | 27 | 25 | Power supply | Negative power supply. This pin is the most negative power supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Voltage | Supply | VDD | –0.3 | 40 | V |
VSS | –40 | 0.3 | |||
VDD – VSS | 40 | ||||
Digital pins(2): EN, A0, A1, A2, A3 | VSS – 0.3 | VDD + 0.3 | |||
Analog pins(2): Sx, SxA, SxB, D, DA, DB | VSS – 2 | VDD + 2 | |||
Current(3) | –30 | 30 | mA | ||
Temperature | Operating, TA | –55 | 150 | °C | |
Junction, TJ | 150 | ||||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | 2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | 500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VDD(1) | Positive power-supply voltage | Dual supply | 5 | 18 | V | |
Single supply | 10 | 36 | ||||
VSS(2) | Negative power-supply voltage (dual supply) | –5 | –18 | V | ||
VDD – VSS | Supply voltage | 10 | 36 | V | ||
VS | Source pins voltage(3) | VSS | VDD | V | ||
VD | Drain pins voltage | VSS | VDD | V | ||
VEN | Enable pin voltage | VSS | VDD | V | ||
VA | Address pins voltage | VSS | VDD | V | ||
ICH | Channel current (TA = 25°C) | –25 | 25 | mA | ||
TA | Operating temperature | –40 | 125 | °C |
THERMAL METRIC(1) | MUX36S16/ MUX36D08 | UNIT | ||||
---|---|---|---|---|---|---|
PW (TSSOP) | DW (SOIC) | RTV (WQFN) | RSN (WQFN) | |||
28 PINS | 28 PINS | 32 PINS | 32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 79.8 | 53.6 | 33.0 | 33.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 24.0 | 30.1 | 20.8 | 26.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 37.6 | 28.5 | 13.9 | 13.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.2 | 9.0 | 0.3 | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 37.1 | 28.4 | 13.8 | 13.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | 4.1 | 4.1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
ANALOG SWITCH | ||||||||
Analog signal range | TA = –40°C to +125°C | VSS | VDD | V | ||||
RON | On-resistance | VS = 0 V, IS = –1 mA | 125 | 170 | Ω | |||
VS = ±10 V, IS = –1 mA | 145 | 200 | ||||||
TA = –40°C to +85°C | 230 | |||||||
TA = –40°C to +125°C | 250 | |||||||
ΔRON | On-resistance mismatch between channels | VS = ±10 V, IS = –1 mA | 6 | 9 | Ω | |||
TA = –40°C to +85°C | 14 | |||||||
TA = –40°C to +125°C | 16 | |||||||
RFLAT | On-resistance flatness | VS = 10 V, 0 V, –10 V | 20 | 45 | Ω | |||
TA = –40°C to +85°C | 53 | |||||||
TA = –40°C to +125°C | 58 | |||||||
On-resistance drift | VS = 0 V | 0.62 | Ω/°C | |||||
IS(OFF) | Input leakage current | Switch state is off,
VS = ±10 V, VD = ±10 V(2) |
–0.04 | 0.001 | 0.04 | nA | ||
TA = –40°C to +85°C | –0.15 | 0.15 | ||||||
TA = –40°C to +125°C | –1.2 | 1.2 | ||||||
ID(OFF) | Output off-leakage current | Switch state is off,
VS = ±10 V, VD = ±10 V(2) |
–0.15 | 0.01 | 0.15 | nA | ||
TA = -40°C to +85°C | –1 | 1 | ||||||
TA = -40°C to +125°C | –4.5 | 4.5 | ||||||
ID(ON) | Output on-leakage current | Switch state is on,
VD = ±10 V, VS = floating |
–0.2 | 0.01 | 0.2 | nA | ||
TA = –40°C to +85°C | –1 | 1 | ||||||
TA = –40°C to +125°C | –5.3 | 5.3 | ||||||
IDL(ON) | Differential on-leakage current | Switch state is on,
VDA = VDB = ±10 V, VS = floating |
–15 | 3 | 15 | pA | ||
TA = –40°C to +85°C | –100 | 100 | ||||||
TA = –40°C to +125°C | –500 | 500 | ||||||
LOGIC INPUT | ||||||||
VIH | Logic voltage high | 2 | V | |||||
VIL | Logic voltage low | 0.8 | V | |||||
ID | Input current | 0.1 | µA | |||||
SWITCH DYNAMICS(1) | ||||||||
tON | Enable turn-on time | VS = ±10 V, RL = 300 Ω,
CL= 35 pF |
82 | 136 | ns | |||
TA = –40°C to +85°C | 145 | |||||||
TA = –40°C to +125°C | 151 | |||||||
tOFF | Enable turn-off time | VS = ±10 V, RL = 300 Ω,
CL= 35 pF |
63 | 78 | ns | |||
TA = –40°C to +85°C | 89 | |||||||
TA = –40°C to +125°C | 97 | |||||||
tt | Transition time | VS = 10 V, RL = 300 Ω,
CL= 35 pF, |
97 | 143 | ns | |||
TA = –40°C to +85°C | 151 | |||||||
TA = –40°C to +125°C | 157 | |||||||
tBBM | Break-before-make time delay | VS = 10 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C | 30 | 54 | ns | |||
QJ | Charge injection | CL = 1 nF, RS = 0 Ω | VS = 0 V | TSSOP package | 0.31 | pC | ||
SOIC package | 0.67 | |||||||
VS = –15 V to +15 V | TSSOP package | ±0.9 | ||||||
SOIC package | ±1.1 | |||||||
Off-isolation | RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz |
Nonadjacent channel to D, DA, DB | TSSOP package | –98 | dB | |||
SOIC package | –94 | |||||||
Adjacent channel to D, DA, DB | TSSOP package | –94 | ||||||
SOIC package | –88 | |||||||
Channel-to-channel crosstalk | RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz |
Nonadjacent channels | TSSOP package | –100 | dB | |||
SOIC package | –96 | |||||||
Adjacent channels | TSSOP package | –88 | ||||||
SOIC package | –83 | |||||||
BW | –3dB Bandwidth | VS = 1 VRMS, RL = 50 Ω , CL = 5 pF | MUX36S16 | 260 | dB | |||
MUX36D08 | 430 | |||||||
THD + N | Total harmonic distortion plus noise | VS = 0 V or VDD, RL = 600 Ω , CL = 50 pF, f = 20Hz to 20kHz | 0.09% | |||||
CIN | Digital input capacitance | VIN = 0 V or VDD | 1.1 | pF | ||||
CS(OFF) | Input off-capacitance | f = 1 MHz, VS = 0 V | 2.1 | 3 | pF | |||
CD(OFF) | Output off-capacitance | f = 1 MHz, VS = 0 V | MUX36S16 | 11.1 | 12.2 | pF | ||
MUX36D08 | 6.4 | 7.5 | ||||||
CS(ON), CD(ON) | Output on-capacitance | f = 1 MHz, VS = 0 V | MUX36S16 | 13.5 | 15 | pF | ||
MUX36D08 | 8.7 | 10.2 | ||||||
POWER SUPPLY | ||||||||
VDD supply current | All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V, |
45 | 59 | µA | ||||
TA = –40°C to +85°C | 62 | |||||||
TA = –40°C to +125°C | 69 | |||||||
VSS supply current | All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V, |
26 | 33 | µA | ||||
TA = –40°C to +85°C | 36 | |||||||
TA = –40°C to +125°C | 43 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
ANALOG SWITCH | ||||||||
Analog signal range | TA = –40°C to +125°C | VSS | VDD | V | ||||
RON | On-resistance | VS = 10 V, IS = –1 mA | 235 | 340 | Ω | |||
TA = –40°C to +85°C | 390 | |||||||
TA = –40°C to +125°C | 430 | |||||||
ΔRON | On-resistance match | VS = 10 V, IS = –1 mA | 7 | 20 | Ω | |||
TA = –40°C to +85°C | 35 | |||||||
TA = –40°C to +125°C | 40 | |||||||
On-resistance drift | VS = 10 V | 1.07 | Ω/°C | |||||
IS(OFF) | Input leakage current | Switch state is off,
VS = 1 V and VD = 10 V, or VS = 10 V and VD = 1 V(1) |
–0.04 | 0.001 | 0.04 | nA | ||
TA = –40°C to +85°C | –0.15 | 0.15 | ||||||
TA = –40°C to +125°C | –1.2 | 1.2 | ||||||
ID(OFF) | Output off leakage current | Switch state is off,
VS = 1 V and VD = 10 V, or VS = 10 V and VD = 1 V(1) |
–0.15 | 0.01 | 0.15 | nA | ||
TA = –40°C to +85°C | –0.75 | 0.75 | ||||||
TA = –40°C to +125°C | –2.4 | 2.4 | ||||||
ID(ON) | Output on leakage current | Switch state is on,
VD = 1 V and 10 V, VS = floating |
–0.15 | 0.01 | 0.15 | nA | ||
TA = –40°C to +85°C | –0.75 | 0.75 | ||||||
TA = –40°C to +125°C | –2.5 | 2.5 | ||||||
IDL(ON) | Differential on-leakage current | Switch state is on,
VDA = VDB = 1 V and 10 V, VS = floating |
–15 | 3 | 15 | pA | ||
TA = –40°C to +85°C | –100 | 100 | ||||||
TA = –40°C to +125°C | –500 | 500 | ||||||
LOGIC INPUT | ||||||||
VIH | Logic voltage high | 2.0 | V | |||||
VIL | Logic voltage low | 0.8 | V | |||||
ID | Input current | 0.1 | µA | |||||
SWITCH DYNAMIC CHARACTERISTICS(2) | ||||||||
tON | Enable turn-on time | VS = 8 V, RL = 300 Ω,
CL= 35 pF |
90 | 145 | ns | |||
TA = –40°C to +85°C | 145 | |||||||
TA = –40°C to +125°C | 149 | |||||||
tOFF | Enable turn-off time | VS = 8 V, RL = 300 Ω,
CL= 35 pF |
66 | 84 | ns | |||
TA = –40°C to +85°C | 94 | |||||||
TA = –40°C to +125°C | 102 | |||||||
tt | Transition time | VS = 8 V, CL= 35 pF | 107 | 147 | ns | |||
VS = 8 V, RL = 300 Ω,
CL= 35 pF, |
TA = –40°C to +85°C | 153 | ||||||
VS = 8 V, RL = 300 Ω,
CL= 35 pF, |
TA = –40°C to +125°C | 155 | ||||||
tBBM | Break-before-make time delay | VS = 8 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C | 30 | 54 | ns | |||
QJ | Charge injection | CL = 1 nF, RS = 0 Ω | VS = 6 V | TSSOP package | 0.12 | pC | ||
SOIC package | 0.38 | |||||||
VS = 0 V to 12 V | TSSOP | ±0.17 | ||||||
SOIC package | ±0.48 | |||||||
Off-isolation | RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz |
Nonadjacent channel to D, DA, DB | TSSOP package | –97 | dB | |||
SOIC package | –94 | |||||||
Adjacent channel to D, DA, DB | TSSOP package | –94 | ||||||
SOIC package | –88 | |||||||
Channel-to-channel crosstalk | RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz |
Nonadjacent channels | TSSOP package | –100 | dB | |||
SOIC package | –99 | |||||||
Adjacent channels | TSSOP | -88 | ||||||
SOIC package | -83 | |||||||
CS(OFF) | Input off-capacitance | f = 1 MHz, VS = 6 V | 2.4 | 3.4 | pF | |||
CD(OFF) | Output off-capacitance | f = 1 MHz, VS = 6 V | MUX36S16 | 14 | 15.4 | pF | ||
MUX36D08 | 7.8 | 9.1 | ||||||
CS(ON), CD(ON) | Output on-capacitance | f = 1 MHz, VS = 6 V | MUX36S16 | 16.2 | 18 | pF | ||
MUX36D08 | 9.9 | 11.6 | ||||||
POWER SUPPLY | ||||||||
VDD supply current | All VA = 0 V or 3.3 V,
VS= 0 V, VEN = 3.3 V |
41 | 59 | µA | ||||
TA = –40°C to +85°C | 56 | |||||||
TA = –40°C to +125°C | 62 | |||||||
VSS supply current | All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V |
22 | 29 | µA | ||||
TA = –40°C to +85°C | 31 | |||||||
TA = –40°C to +125°C | 37 |
VDD = 24 V, VSS = 0 V |
VDD = 15 V, VSS = –15 V |
MUX36S16, source-to-drain |
Drain-to-source |
MUX36S16, VDD = 15 V, VSS = –15 V |
MUX36S16, VDD = 30 V, VSS = 0 V |
MUX36S16, VDD = 12 V, VSS = 0 V |
VDD = 15 V, VSS = –15 V |
VDD = 12 V, VSS = 0 V |
VDD = 12 V, VSS = –12 V |
VDD = 12 V, VSS = 0 V |
MUX36D08, source-to-drain |
MUX36D08, VDD = 15 V, VSS = –15 V |
MUX36D08, VDD = 30 V, VSS = 0 V |
MUX36D08, VDD = 12 V, VSS = 0 V |
EN | A3 | A2 | A1 | A0 | ON-CHANNEL |
---|---|---|---|---|---|
0 | X(1) | X(1) | X(1) | X(1) | All channels are off |
1 | 0 | 0 | 0 | 0 | Channel 1 |
1 | 0 | 0 | 0 | 1 | Channel 2 |
1 | 0 | 0 | 1 | 0 | Channel 3 |
1 | 0 | 0 | 1 | 1 | Channel 4 |
1 | 0 | 1 | 0 | 0 | Channel 5 |
1 | 0 | 1 | 0 | 1 | Channel 6 |
1 | 0 | 1 | 1 | 0 | Channel 7 |
1 | 0 | 1 | 1 | 1 | Channel 8 |
1 | 1 | 0 | 0 | 0 | Channel 9 |
1 | 1 | 0 | 0 | 1 | Channel 10 |
1 | 1 | 0 | 1 | 0 | Channel 11 |
1 | 1 | 0 | 1 | 1 | Channel 12 |
1 | 1 | 1 | 0 | 0 | Channel 13 |
1 | 1 | 1 | 0 | 1 | Channel 14 |
1 | 1 | 1 | 1 | 0 | Channel 15 |
1 | 1 | 1 | 1 | 1 | Channel 16 |
EN | A2 | A1 | A0 | ON-CHANNEL |
---|---|---|---|---|
0 | X(1) | X(1) | X(1) | All channels are off |
1 | 0 | 0 | 0 | Channels 1A and 1B |
1 | 0 | 0 | 1 | Channels 2A and 2B |
1 | 0 | 1 | 0 | Channels 3A and 3B |
1 | 0 | 1 | 1 | Channels 4A and 4B |
1 | 1 | 0 | 0 | Channels 5A and 5B |
1 | 1 | 0 | 1 | Channels 6A and 6B |
1 | 1 | 1 | 0 | Channels 7A and 7B |
1 | 1 | 1 | 1 | Channels 8A and 8B |
The on-resistance of the MUX36xxx is the ohmic resistance across the source (Sx, SxA, or SxB) and drain (D, DA, or DB) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance. The measurement setup used to measure RON is shown in Figure 26. Voltage (V) and current (ICH) are measured using this setup, and RON is computed as shown in Equation 1:
There are two types of leakage currents associated with a switch during the OFF state:
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off. This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 27
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in the ON state. The source pin is left floating during the measurement. Figure 28 shows the circuit used for measuring the on-leakage current, denoted by ID(ON).
In case of a differential signal, the on-leakage current is defined as the differential leakage current that flows into, or out of, the drain pins when the switches are in the ON state. The source pins are left floating during the measurement. Figure 29 shows the circuit used for measuring the on-leakage current on each signal path, denoted by IDA(ON) and IDB(ON). The absolute difference between these two currents is defined as the differential on-leakage current, denoted by IDL(ON).
Transition time is defined as the time taken by the output of the MUX36xxx to rise or fall to 90% of the transition after the digital address signal has fallen or risen to 50% of the transition. Figure 30 shows the setup used to measure transition time, denoted by the symbol tt.
Break-before-make delay is a safety feature that prevents two inputs from connecting when the MUX36xxx is switching. The MUX36xxx output first breaks from the ON-state switch before making the connection with the next ON-state switch. The time delay between the break and the make is known as break-before-make delay. Figure 31 shows the setup used to measure break-before-make delay, denoted by the symbol tBBM.
Turn-on time is defined as the time taken by the output of the MUX36xxx to rise to 90% final value after the enable signal has risen to 50% final value. Figure 32 shows the setup used to measure turn-on time. Turn-on time is denoted by the symbol tON.
Turn off time is defined as the time taken by the output of the MUX36xxx to fall to 10% initial value after the enable signal has fallen to 50% initial value. Figure 32 shows the setup used to measure turn-off time. Turn-off time is denoted by the symbol tOFF.
The MUX36xxx have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted by the symbol QINJ. Figure 33 shows the setup used to measure charge injection.
Off isolation is defined as the voltage at the drain pin (D, DA, or DB) of the MUX36xxx when a 1-VRMS signal is applied to the source pin (Sx, SxA, or SxB) of an off-channel. Figure 34 shows the setup used to measure off isolation. Use Equation 2 to compute off isolation.
Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx, SxA, or SxB) of an off-channel, when a 1-VRMS signal is applied at the source pin of an on-channel. Figure 35 shows the setup used to measure channel-to-channel crosstalk. Use Equation 3 to compute, channel-to-channel crosstalk.
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied to the source pin of an on-channel, and the output measured at the drain pin of the MUX36xxx. Figure 36 shows the setup used to measure bandwidth of the mux. Use Equation 4 to compute the attenuation.
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux output. The on-resistance of the MUX36xxx varies with the amplitude of the input signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as THD+N. Figure 37 shows the setup used to measure THD+N of the MUX36xxx.
The MUX36xxx are a family of analog multiplexers. The Functional Block Diagram section provides a top-level block diagram of both the MUX36S16 and MUX36D08. The MUX36S16 is a 16-channel, single-ended, analog mux. The MUX36D08 is an 8-channel, differential or dual 8:1, single-ended, analog mux. Each channel is turned on or turned off based on the state of the address lines and enable pin.
The MUX36xxx provide extremely low on- and off-leakage currents. The MUX36xxx are capable of switching signals from high source-impedance inputs into a high input-impedance op amp with minimal offset error because of the ultra-low leakage currents. Figure 38 shows typical leakage currents of the MUX36xxx versus temperature.
The MUX36xxx have a simple transmission gate topology, as shown in Figure 39. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
The MUX36xxx have special charge-injection cancellation circuitry that reduces the source-to-drain charge injection to as low as 0.31 pC at VS = 0 V, and ±0.9 pC in the full signal range, as shown in Figure 40.
The drain-to-source charge injection becomes important when the device is used as a demultiplexer (demux), where D becomes the input and Sx becomes the output. Figure 41 shows the drain-to-source charge injection across the full signal range.
The MUX36xxx are operable as both a mux and demux. The source (Sx, SxA, SxB) and drain (D, DA, DB) pins of the MUX36xxx are used either as input or output. Each MUX36xxx channel has very similar characteristics in both directions.
The valid analog signal for the MUX36xxx ranges from VSS to VDD. The input signal to the MUX36xxx swings from VSS to VDD without any significant degradation in performance. The on-resistance of the MUX36xxx varies with input signal, as shown in Figure 42
When the EN pin of the MUX36xxx is pulled high, one of the switches is closed based on the state of the address lines. When the EN pin is pulled low, all the switches are in an open state irrespective of the state of the address lines. The EN pin can be connected to VDD (as high as 36 V).
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The MUX36xxx family offers outstanding input/output leakage currents and ultra-low charge injection. These devices operate up to 36 V, and offer true rail-to-rail input and output. The on-capacitance of the MUX36xxx is very low. These features makes the MUX36xxx a family of precision, robust, high-performance analog multiplexer for high-voltage, industrial applications.
Figure 43 shows a 16-bit, differential, 8-channel, multiplexed, data-acquisition system. This example is typical in industrial applications that require low distortion and a high-voltage differential input. The circuit uses the ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential mux. This TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the MUX36D08, OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
The primary objective is to design a ±20 V, differential, 8-channel, multiplexed, data-acquisition system with lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure, sine-wave input. The design requirements for this block design are:
The purpose of this precision design is to design an optimal, high-voltage, multiplexed, data-acquisition system for highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 43. The circuit is a multichannel, data-acquisition signal chain consisting of an input low-pass filter, mux, mux output buffer, attenuating SAR ADC driver, and the reference driver. The architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. Detailed design considerations and component selection procedure can be found in the TI Precision Design TIPD151, 16-Bit, 400-kSPS, 4-Channel Multiplexed Data-Acquisition System for High-Voltage Inputs with Lowest Distortion.
The MUX36xxx operates across a wide supply range of ±5 V to ±18 V (10 V to 36 V in single-supply mode). The devices also perform well with unsymmetric supplies such as VDD = 12 V and VSS= –5 V. For reliable operation, use a supply decoupling capacitor ranging between 0.1 µF to 10 µF at both the VDD and VSS pins to ground.
The on-resistance of the MUX36xxx varies with supply voltage, as illustrated in Figure 45
Figure 46 illustrates an example of a PCB layout with the MUX36S16IPW, and Figure 47 illustrates an example of a PCB layout with MUX36D08IPW.
Some key considerations are:
For related documentation see the following:
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now.
PARTS | PRODUCT FOLDER | ORDER NOW | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
MUX36S16 | Click here | Click here | Click here | Click here | Click here |
MUX36D08 | Click here | Click here | Click here | Click here | Click here |
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