SBAS803A November 2016 – November 2017 MUX506 , MUX507
PRODUCTION DATA.
The MUX50x are a family of analog multiplexers. The Functional Block Diagram section provides a top-level block diagram of both the MUX506 and MUX507. The MUX506 is a 16-channel, single-ended, analog mux. The MUX507 is an 8-channel, differential or dual 8:1, single-ended, analog mux. Each channel is turned on or turned off based on the state of the address lines and enable pin.
The MUX50x provide extremely low on- and off-leakage currents. The MUX50x are capable of switching signals from high source-impedance inputs into a high input-impedance op amp with minimal offset error because of the ultra-low leakage currents. Figure 37 shows typical leakage currents of the MUX50x versus temperature.
The MUX50x have a simple transmission gate topology, as shown in Figure 38. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
The MUX50x have special charge-injection cancellation circuitry that reduces the source-to-drain charge injection to as low as 0.31 pC at VS = 0 V, and ±0.9 pC in the full signal range, as shown in Figure 39.
The drain-to-source charge injection becomes important when the device is used as a demultiplexer (demux), where D becomes the input and Sx becomes the output. Figure 40 shows the drain-to-source charge injection across the full signal range.
The MUX50x are operable as both a mux and demux. The source (Sx, SxA, SxB) and drain (D, DA, DB) pins of the MUX50x are used either as input or output. Each MUX50x channel has very similar characteristics in both directions.
The valid analog signal for the MUX50x ranges from VSS to VDD. The input signal to the MUX50x swings from VSS to VDD without any significant degradation in performance. The on-resistance of the MUX50x varies with input signal, as shown in Figure 41
When the EN pin of the MUX50x is pulled high, one of the switches is closed based on the state of the address lines. When the EN pin is pulled low, all the switches are in an open state irrespective of the state of the address lines. The EN pin can be connected to VDD (as high as 36 V).