6.1.1 Parameter Information Device-Specific Information

A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal.

Figure 6-1 Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

6.1.1.1 Signal Transition Levels

All input and output timing parameters are referenced to V_ref for both "0" and "1" logic levels.

For 3.3 V I/O, V_ref = 1.65 V.

For 1.8 V I/O, V_ref = 0.9 V.

For 1.2 V I/O, V_ref = 0.6 V.

Figure 6-2 Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to V_IL MAX and V_IH MIN for input clocks, V_OLMAX and V_OH MIN for output clocks

Figure 6-3 Rise and Fall Transition Time Voltage Reference Levels

6.3.1 Power-On Sequence

The device should be powered-on in the following order:

1. RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other supplies being applied or powered-up at the same time as CVDD. If the RTC is not used, RTC_CVDD should be connected to CVDD. RTC_CVDD should not be left unpowered while CVDD is powered.
2. Core logic supplies:
   1. All variable 1.2V - 1.0V core logic supplies (CVDD)
   2. All static core logic supplies (RVDD, PLL0_VDDA, PLL1_VDDA, USB_CVDD). If voltage scaling is not used on the device, groups 2a) and 2b) can be controlled from the same power supply and powered up together.
3. All static 1.8V IO supplies (DVDD18, DDR_DVDD18, and USB0_VDDA18 ) and any of the LVCMOS IO supply groups used at 1.8V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C).
4. LVCMOS IO supply groups used at 3.3V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C).

There is no specific required voltage ramp rate for any of the supplies as long as the LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8V supplies by more than 2 volts.

RESET must be maintained active until all power supplies have reached their nominal values.

6.3.2 Power-Off Sequence

The power supplies can be powered-off in any order as long as LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed static 1.8V supplies by more than 2 volts. There is no specific required voltage ramp down rate for any of the supplies (except as required to meet the above mentioned voltage condition).

6.4.1 Power-On Reset (POR)

A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal logic to its default state. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence, and RTCK/GP8[0]. If an emulator is driving TCK into the device during reset, then RTCK/GP8[0] will drive out RTCK. If TCK is not being driven into the device during reset, then RTCK/GP8[0] will drive low. RESETOUT in an output for use by other controllers in the system that indicates the device is currently in reset.

While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and device's emulation logic in the reset state.

TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.

RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will always be asserted upon power up and the device's internal emulation logic will always be properly initialized.

JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.

RTCK/GP8[0] is maintained active through a POR.

A summary of the effects of Power-On Reset is given below:

• All internal logic (including emulation logic and the PLL logic) is reset to its default state
• Internal memory is not maintained through a POR
• RESETOUT goes active
• All device pins go to a high-impedance state
• The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC

CAUTION: A watchdog reset triggers a POR.

6.4.2 Warm Reset

A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low (TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence, and RTCK/GP8[0]. If an emulator is driving TCK into the device during reset, then RTCK/GP8[0] will drive out RTCK. If TCK is not being driven into the device during reset, then RTCK/GP8[0] will drive low. RESETOUT is an output for use by other controllers in the system that indicates the device is currently in reset.

During an emulation, the emulator will maintain TRST high and hence only warm reset (not POR) is available during emulation debug and development.

RTCK/GP8[0] is maintained active through a warm reset.

A summary of the effects of Warm Reset is given below:

• All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
• Internal memory is maintained through a warm reset
• RESETOUT goes active
• All device pins go to a high-impedance state
• The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the RTC

6.4.3 Reset Electrical Data Timings

Table 6-1 assumes testing over the recommended operating conditions.

Figure 6-4 Power-On Reset (RESET and TRST active) Timing

Figure 6-5 Warm Reset (RESET active, TRST high) Timing

Table 6-2 Oscillator Timing Requirements

Table 6-3 OSCIN Timing Requirements for an Externally Driven Clock

6.6.1 PLL Device-Specific Information

The device DSP generates the high-frequency internal clocks it requires through an on-chip PLL.

The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-8.

Figure 6-8 PLL External Filtering Components

The external filtering components shown above provide noise immunity for the PLLs. PLL0_VDDA and PLL1_VDDA should not be connected together to provide noise immunity between the two PLLs. Likewise, PLL0_VSSA and PLL1_VSSA should not be connected together.

The input to the PLL is either from the on-chip oscillator or from an external clock on the OSCIN pin. PLL0 outputs seven clocks that have programmable divider options. PLL1 outputs three clocks that have programmable divider options. Figure 6-9 illustrates the high-level view of the PLL Topology.

The PLLs are disabled by default after a device reset. They must be configured by software according to the allowable operating conditions listed in Table 6-4 before enabling the device to run from the PLL by setting PLLEN = 1.

Table 6-4 Allowed PLL Operating Conditions (PLL0 and PLL1)

NO.	PARAMETER	Default Value	MIN	MAX	UNIT
1	PLLRST: Assertion time during initialization	N/A	1000	N/A	ns
2	Lock time: The time that the application has to wait for the PLL to acquire lock before setting PLLEN, after changing PREDIV, PLLM, or OSCIN	N/A	N/A	(1)	OSCIN cycles
3	PREDIV: Pre-divider value	/1	/1	/32	-
4	PLLREF: PLL input frequency		12	30 (if internal oscillator is used) 50 (if external clock is used)	MHz
5	PLLM: PLL multiplier values	x20	x4	x32
6	PLLOUT: PLL output frequency	N/A	200	600	MHz
7	POSTDIV: Post-divider value	/1	/1	/32	-

6.6.2 Device Clock Generation

PLL0 is controlled by PLL Controller 0 and PLL1 is controlled by PLL Controller 1. PLLC0 and PLLC1 manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test points.

PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the DDR2/mDDR Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on the application requirements. In addition, some peripherals have specific clock options independent of the ASYNC clock domain.

6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)

The processor supports multiple operating points by scaling voltage and frequency to minimize power consumption for a given level of processor performance.

Frequency scaling is achieved by modifying the setting of the PLL controllers’ multipliers, post-dividers (POSTDIV), and system clock dividers (SYSCLKn). Modification of the POSTDIV and SYSCLK values does not require relocking the PLL and provides lower latency to switch between operating points, but at the expense of the frequencies being limited by the integer divide values (only the divide values are altered the PLL multiplier is left unmodified). Non integer divide frequency values can be achieved by changing both the multiplier and the divide values, but when the PLL multiplier is changed the PLL must relock, incurring additional latency to change between operating points. Detailed information on modifying the PLL Controller settings can be found in the OMAP-L132 C6-Integra DSP+ARM Technical Reference Manual (SPRUH78).

Voltage scaling is enabled from outside the device by controlling an external voltage regulator. The processor may communicate with the regulator using GPIOs, I2C or some other interface. When switching between voltage-frequency operating points, the voltage must always support the desired frequency. When moving from a high-performance operating point to a lower performance operating point, the frequency should be lowered first followed by the voltage. When moving from a low-performance operating point to a higher performance operating point, the voltage should be raised first followed by the frequency. Voltage operating points refer to the CVdd voltage at that point. Other static supplies must be maintained at their nominal voltages at all operating points.

The maximum voltage slew rate for CVdd supply changes is 1 mV/us.

For additional information on power management solutions from TI for this processor, follow the Power Management link in the Product Folder on www.ti.com for this processor.

The processor supports multiple clock domains some of which have clock ratio requirements to each other. SYSCLK1:SYSCLK2:SYSCLK4:SYSCLK6 are synchronous to each other and the SYSCLKn dividers must always be configured such that the ratio between these domains is 1:2:4:1. The ASYNC and ASYNC3 clock domains are asynchronous to the other clock domains and have no specific ratio requirement.

Table 6-5 summarizes the maximum internal clock frequencies at each of the voltage operating points.

Some interfaces have specific limitations on supported modes/speeds at each operating point. See the corresponding peripheral sections of this document for more information.

TI provides software components (called the Power Manager) to perform DVFS and abstract the task from the user. The Power Manager controls changing operating points (both frequency and voltage) and handles the related tasks involved such as informing/controlling peripherals to provide graceful transitions between operating points. The Power Manager is bundled as a component of DSP/BIOS.

6.7.1 ARM CPU Interrupts

The ARM9 CPU core supports two direct interrupts: FIQ and IRQ. The ARM Interrupt Controller (AINTC) extends the number of interrupts to 100, and provides features like programmable masking, priority, hardware nesting support, and interrupt vector generation.

6.7.2 DSP Interrupts

The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable and is listed in Table 6-8. Also, the interrupt controller controls the generation of the CPU exceptions, NMI, and emulation interrupts. Table 6-9 summarizes the C674x interrupt controller registers and memory locations.

Refer to the C674x DSP MegaModule Reference Guide (SPRUFK5) and the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8) for details of the C674x interrupts.

Table 6-10 Power and Sleep Controller (PSC) Registers

6.8.1 Power Domain and Module Topology

The device includes two PSC modules.

Each PSC module controls clock states for several of the on chip modules, controllers and interconnect components. Table 6-11 and Table 6-12 lists the set of peripherals/modules that are controlled by the PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset) module states. The module states and terminology are defined in Section 6.8.1.2.

6.9.1 EDMA3 Channel Synchronization Events

Each EDMA3 channel controller supports up to 32 channels which service peripherals and memory. Table 6-14 lists the source of the EDMA3 synchronization events associated with each of the programmable EDMA channels.

6.9.2 EDMA3 Peripheral Register Descriptions

Table 6-15 is the list of EDMA3 Channel Controller Registers and Table 6-16 is the list of EDMA3 Transfer Controller registers.

Table 6-17 shows an abbreviation of the set of registers which make up the parameter set for each of 128 EDMA3 events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-18 shows the parameter set entry registers with relative memory address locations within each of the parameter sets.

6.10.1 EMIFA Asynchronous Memory Support

EMIFA supports asynchronous:

• SRAM memories
• NAND Flash memories
• NOR Flash memories

The EMIFA data bus width is up to 16-bits.The device supports up to 23 address lines and two external wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIFA (EMA_CS[5:2]).

Each chip select has the following individually programmable attributes:

• Data Bus Width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turn around time
• Extended Wait Option With Programmable Timeout
• Select Strobe Option
• NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.

6.10.2 EMIFA Synchronous DRAM Memory Support

The device supports 16-bit SDRAM in addition to the asynchronous memories listed in Section 6.10.1. It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are supported are:

• One, Two, and Four Bank SDRAM devices
• Devices with Eight, Nine, Ten, and Eleven Column Address
• CAS Latency of two or three clock cycles
• Sixteen Bit Data Bus Width

Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory contents; since the SDRAM will continue to refresh itself even without clocks from the device. Powerdown mode achieves even lower power, except the device must periodically wake the SDRAM up and issue refreshes if data retention is required.

Finally, note that the EMIFA does not support Mobile SDRAM devices.

Table 6-19 shows the supported SDRAM configurations for EMIFA.

6.10.3 EMIFA SDRAM Loading Limitations

EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads. Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by board simulation using IBIS models.

6.10.4 EMIFA Connection Examples

Figure 6-10 illustrates an example of how SDRAM, NOR, and NAND flash devices might be connected to EMIFA simultaneously. The SDRAM chip select must be EMA_CS[0]. Note that the NOR flash is connected to EMA_CS[2] and the NAND flash is connected to EMA_CS[3] in this example. Note that any type of asynchronous memory may be connected to EMA_CS[5:2].

The on-chip bootloader makes some assumptions on which chip select the contains the boot image, and this depends on the boot mode. For NOR boot mode; the on-chip bootloader requires that the image be stored in NOR flash on EMA_CS[2]. For NAND boot mode, the bootloader requires that the boot image is stored in NAND flash on EMA_CS[3]. It is always possible to have the image span multiple chip selects, but this must be supported by second stage boot code stored in the external flash.

A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 6-11. This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to bootload it.

Figure 6-10 Connection Diagram: SDRAM, NOR, NAND

Figure 6-11 EMIFA Connection Diagram: Multiple NAND Flash Planes

6.10.5 External Memory Interface Register Descriptions

6.10.6 EMIFA Electrical Data/Timing

Table 6-21 through Table 6-24 assume testing over recommended operating conditions.

Figure 6-12 EMIFA Basic SDRAM Write Operation

Figure 6-13 EMIFA Basic SDRAM Read Operation

Figure 6-14 Asynchronous Memory Read Timing for EMIFA

Figure 6-15 Asynchronous Memory Write Timing for EMIFA

Figure 6-16 EMA_WAIT Read Timing Requirements

Figure 6-17 EMA_WAIT Write Timing Requirements

6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing

6.11.2 DDR2/mDDR Memory Controller Register Description(s)

6.11.3 DDR2/mDDR Interface

This section provides the timing specification for the DDR2/mDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR memory system without the need for a complex timing closure process. For more information regarding guidelines for using this DDR2/mDDR specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).

1. See Figure 6-25 for DQGATE routing specifications.

2. For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR, these capacitors can be eliminated completely.

3. VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.

Figure 6-18 DDR2/mDDR Single-Memory High Level Schematic

1. See Figure 6-25 for DQGATE routing specifications.

2. For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR, these capacitors can be eliminated completely.

3. VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.

Figure 6-19 DDR2/mDDR Dual-Memory High Level Schematic

6.11.3.4 Placement

Figure 6-19 shows the required placement for the device as well as the DDR2/mDDR devices. The dimensions for Figure 6-20 are defined in Table 6-30. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2/mDDR systems, the second DDR2/mDDR device is omitted from the placement.

Figure 6-20 OMAP-L132 and DDR2/mDDR Device Placement

Table 6-30 Placement Specifications⁽¹⁾⁽²⁾

NO.	PARAMETER	MIN	MAX	UNIT
1	X		1750	Mils
2	Y		1280	Mils
3	Y Offset	(3)	650	Mils
4	Clearance from non-DDR2/mDDR signal to DDR2/mDDR Keepout Region(4)	4		w(5)

(1) See Figure 6-20 for dimension definitions.

(2) Measurements from center of device to center of DDR2/mDDR device.

(3) For single memory systems it is recommended that Y Offset be as small as possible.

(4) Non-DDR2/mDDR signals allowed within DDR2/mDDR keepout region provided they are separated from DDR2/mDDR routing layers by a ground plane.

(5) w = PCB trace width as defined in Table 6-29.

6.11.3.5 DDR2/mDDR Keep Out Region

The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 6-21. The size of this region varies with the placement and DDR routing. Additional clearances required for the keep out region are shown in Table 6-30.

Figure 6-21 DDR2/mDDR Keepout Region

6.11.3.10 VREF Routing

VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the OMAP-L132. VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a resistive divider as shown in Figure 6-18. Other methods of creating VREF are not recommended. Figure 6-22 shows the layout guidelines for VREF.

Figure 6-22 VREF Routing and Topology

6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing

Figure 6-23 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized.

Figure 6-23 CK and ADDR_CTRL Routing and Topology

Table 6-36 CK and ADDR_CTRL Routing Specification

NO.	PARAMETER	MIN	TYP	MAX	UNIT
1	Center to Center CK-CKN Spacing(3)			2w(4)
2	CK A to B/A to C Skew Length Mismatch(1)			25	Mils
3	CK B to C Skew Length Mismatch			25	Mils
4	Center to center CK to other DDR2/mDDR trace spacing(3)	4w(4)
5	CK/ADDR_CTRL nominal trace length(2)	CACLM-50	CACLM	CACLM+50	Mils
6	ADDR_CTRL to CK Skew Length Mismatch			100	Mils
7	ADDR_CTRL to ADDR_CTRL Skew Length Mismatch			100	Mils
8	Center to center ADDR_CTRL to other DDR2/mDDR trace spacing(3)	4w(4)
9	Center to center ADDR_CTRL to other ADDR_CTRL trace spacing(3)	3w (4)
10	ADDR_CTRL A to B/A to C Skew Length Mismatch(1)			100	Mils
11	ADDR_CTRL B to C Skew Length Mismatch			100	Mils

(1) Series terminator, if used, should be located closest to device.

(2) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.

(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(4) w = PCB trace width as defined in Table 6-29.

Figure 6-24 shows the topology and routing for the DQS and D net class; the routes are point to point. Skew matching across bytes is not needed nor recommended.

Figure 6-24 DQS and D Routing and Topology

Table 6-37 DQS and D Routing Specification

NO.	PARAMETER	MIN	TYP	MAX	UNIT
1	Center to center DQS to other DDR2/mDDR trace spacing(4)	4w(6)
2	DQS/D nominal trace length(1)(3)	DQLM-50	DQLM	DQLM+50	Mils
3	D to DQS Skew Length Mismatch(3)			100	Mils
4	D to D Skew Length Mismatch(3)			100	Mils
5	Center to center D to other DDR2/mDDR trace spacing(4)(5)	4w(6)
6	Center to Center D to other D trace spacing(4)(2)	3w(6)

(1) Series terminator, if used, should be located closest to DDR.

(2) DQLM is the longest Manhattan distance of each of the DQS and D net class.

(3) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte 1.

(4) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(5) D's from other DQS domains are considered other DDR2/mDDR trace.

(6) w = PCB trace width as defined in Table 6-29.

Figure 6-25 shows the routing for the DQGATE net class. Table 6-38 contains the routing specification.

Figure 6-25 DQGATE Routing

Table 6-38 DQGATE Routing Specification

NO.	PARAMETER	MIN	TYP	MAX	UNIT
1	DQGATE Length F		CKB0B(1)
2	Center to center DQGATE to any other trace spacing	4w(3)
3	DQS/D nominal trace length	DQLM-50	DQLM	DQLM+50	Mils
4	DQGATE Skew(2)			100	Mils

(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.

(2) Skew from CKB0B1

(3) w = PCB trace width as defined in Table 6-29.

Table 6-39 MPU1 Configuration Registers

Table 6-40 MPU2 Configuration Registers

6.13.1 MMCSD Peripheral Description

The device includes an two MMCSD controllers which are compliant with MMC V4.0, Secure Digital Part 1 Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.

The MMC/SD Controller have following features:

• MultiMediaCard (MMC)
• Secure Digital (SD) Memory Card
• MMC/SD protocol support
• SD high capacity support
• SDIO protocol support
• Programmable clock frequency
• 512 bit Read/Write FIFO to lower system overhead
• Slave EDMA transfer capability

The device MMC/SD Controller does not support SPI mode.

6.13.2 MMCSD Peripheral Register Description(s)

6.13.3 MMC/SD Electrical Data/Timing

Table 6-42 through Table 6-43 assume testing over recommended operating conditions.