SPRS563G September   2008  – June 2014 OMAP-L137

PRODUCTION DATA.  

  1. 1 OMAP-L137 Low-Power Applications Processor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 DSP Subsystem
      1. 3.4.1 C674x DSP CPU Description
      2. 3.4.2 DSP Memory Mapping
        1. 3.4.2.1 ARM Internal Memories
        2. 3.4.2.2 External Memories
        3. 3.4.2.3 DSP Internal Memories
        4. 3.4.2.4 C674x CPU
    5. 3.5 Memory Map Summary
    6. 3.6 Pin Assignments
      1. 3.6.1 Pin Map (Bottom View)
    7. 3.7 Terminal Functions
      1. 3.7.1  Device Reset and JTAG
      2. 3.7.2  High-Frequency Oscillator and PLL
      3. 3.7.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.7.4  External Memory Interface A (ASYNC, SDRAM)
      5. 3.7.5  External Memory Interface B (only SDRAM)
      6. 3.7.6  Serial Peripheral Interface Modules (SPI0, SPI1)
      7. 3.7.7  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      8. 3.7.8  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      9. 3.7.9  Enhanced Quadrature Encoder Pulse Module (eQEP)
      10. 3.7.10 Boot
      11. 3.7.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      12. 3.7.12 Inter-Integrated Circuit Modules(I2C0, I2C1)
      13. 3.7.13 Timers
      14. 3.7.14 Universal Host-Port Interface (UHPI)
      15. 3.7.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
      16. 3.7.16 Universal Serial Bus Modules (USB0, USB1)
      17. 3.7.17 Ethernet Media Access Controller (EMAC)
      18. 3.7.18 Multimedia Card/Secure Digital (MMC/SD)
      19. 3.7.19 Liquid Crystal Display Controller (LCD)
      20. 3.7.20 Reserved and No Connect
      21. 3.7.21 Supply and Ground
      22. 3.7.22 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
    4. 4.4 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
    5. 4.5 Handling Ratings
    6. 4.6 Recommended Operating Conditions
    7. 4.7 Notes on Recommended Power-On Hours (POH)
    8. 4.8 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  5. 5Peripheral Information and Electrical Specifications
    1. 5.1  Parameter Information
      1. 5.1.1 Parameter Information Device-Specific Information
        1. 5.1.1.1 Signal Transition Levels
    2. 5.2  Recommended Clock and Control Signal Transition Behavior
    3. 5.3  Power Supplies
      1. 5.3.1 Power-on Sequence
      2. 5.3.2 Power-off Sequence
    4. 5.4  Reset
      1. 5.4.1 Power-On Reset (POR)
      2. 5.4.2 Warm Reset
      3. 5.4.3 Reset Electrical Data Timings
    5. 5.5  Crystal Oscillator or External Clock Input
    6. 5.6  Clock PLLs
      1. 5.6.1 PLL Device-Specific Information
      2. 5.6.2 Device Clock Generation
      3. 5.6.3 PLL Controller 0 Registers
    7. 5.7  Interrupts
      1. 5.7.1 ARM CPU Interrupts
        1. 5.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 5.7.1.2 AINTC Hardware Vector Generation
        3. 5.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 5.7.1.4 AINTC System Interrupt Assignments on OMAP-L137
        5. 5.7.1.5 AINTC Memory Map
      2. 5.7.2 DSP Interrupts
      3. 5.7.3 ARM/DSP Communications Interrupts
    8. 5.8  General-Purpose Input/Output (GPIO)
      1. 5.8.1 GPIO Register Description(s)
      2. 5.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 5.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    9. 5.9  EDMA
    10. 5.10 External Memory Interface A (EMIFA)
      1. 5.10.1 EMIFA Asynchronous Memory Support
      2. 5.10.2 EMIFA Synchronous DRAM Memory Support
      3. 5.10.3 EMIFA SDRAM Loading Limitations
      4. 5.10.4 EMIFA Connection Examples
      5. 5.10.5 External Memory Interface A (EMIFA) Registers
      6. 5.10.6 EMIFA Electrical Data/Timing
    11. 5.11 External Memory Interface B (EMIFB)
      1. 5.11.1 EMIFB SDRAM Loading Limitations
      2. 5.11.2 Interfacing to SDRAM
      3. 5.11.3 EMIFB Electrical Data/Timing
    12. 5.12 Memory Protection Units
    13. 5.13 MMC / SD / SDIO (MMCSD)
      1. 5.13.1 MMCSD Peripheral Description
      2. 5.13.2 MMCSD Peripheral Register Description(s)
      3. 5.13.3 MMC/SD Electrical Data/Timing
    14. 5.14 Ethernet Media Access Controller (EMAC)
      1. 5.14.1 EMAC Peripheral Register Description(s)
    15. 5.15 Management Data Input/Output (MDIO)
      1. 5.15.1 MDIO Registers
      2. 5.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    16. 5.16 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
      1. 5.16.1 McASP Peripheral Registers Description(s)
      2. 5.16.2 McASP Electrical Data/Timing
        1. 5.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
        2. 5.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
        3. 5.16.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
    17. 5.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 5.17.1 SPI Peripheral Registers Description(s)
      2. 5.17.2 SPI Electrical Data/Timing
        1. 5.17.2.1 Serial Peripheral Interface (SPI) Timing
    18. 5.18 Enhanced Capture (eCAP) Peripheral
    19. 5.19 Enhanced Quadrature Encoder (eQEP) Peripheral
    20. 5.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 5.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
      2. 5.20.2 Trip-Zone Input Timing
    21. 5.21 LCD Controller
      1. 5.21.1 LCD Interface Display Driver (LIDD Mode)
      2. 5.21.2 LCD Raster Mode
    22. 5.22 Timers
      1. 5.22.1 Timer Electrical Data/Timing
    23. 5.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 5.23.1 I2C Device-Specific Information
      2. 5.23.2 I2C Peripheral Registers Description(s)
      3. 5.23.3 I2C Electrical Data/Timing
        1. 5.23.3.1 Inter-Integrated Circuit (I2C) Timing
    24. 5.24 Universal Asynchronous Receiver/Transmitter (UART)
      1. 5.24.1 UART Peripheral Registers Description(s)
      2. 5.24.2 UART Electrical Data/Timing
    25. 5.25 USB1 Host Controller Registers (USB1.1 OHCI)
      1. 5.25.1 USB1 Unused Signal Configuration
    26. 5.26 USB0 OTG (USB2.0 OTG)
      1. 5.26.1 USB2.0 Electrical Data/Timing
      2. 5.26.2 USB0 Unused Signal Configuration
    27. 5.27 Host-Port Interface (UHPI)
      1. 5.27.1 HPI Device-Specific Information
      2. 5.27.2 HPI Peripheral Register Description(s)
      3. 5.27.3 HPI Electrical Data/Timing
    28. 5.28 Power and Sleep Controller (PSC)
      1. 5.28.1 Power Domain and Module Topology
        1. 5.28.1.1 Power Domain States
        2. 5.28.1.2 Module States
    29. 5.29 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 5.29.1 PRUSS Register Descriptions
    30. 5.30 Emulation Logic
      1. 5.30.1 JTAG Port Description
      2. 5.30.2 Scan Chain Configuration Parameters
      3. 5.30.3 Initial Scan Chain Configuration
        1. 5.30.3.1 Adding TAPS to the Scan Chain
      4. 5.30.4 JTAG 1149.1 Boundary Scan Considerations
    31. 5.31 IEEE 1149.1 JTAG
      1. 5.31.1 JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
      2. 5.31.2 JTAG Test-Port Electrical Data/Timing
    32. 5.32 Real Time Clock (RTC)
      1. 5.32.1 Clock Source
      2. 5.32.2 Real-Time Clock Registers
  6. 6Device and Documentation Support
    1. 6.1 Device Support
      1. 6.1.1 Development Support
      2. 6.1.2 Device and Development-Support Tool Nomenclature
    2. 6.2 Documentation Support
    3. 6.3 Community Resources
    4. 6.4 Trademarks
    5. 6.5 Electrostatic Discharge Caution
    6. 6.6 Glossary
  7. 7Mechanical Packaging and Orderable Information
    1. 7.1 Thermal Data for ZKB
    2. 7.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZKB|256
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Device Configuration

4.1 Boot Modes

This device supports a variety of boot modes through an internal ROM bootloader. This device does not support dedicated hardware boot modes; therefore, all boot modes utilize the internal ROM. The input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by the values of the BOOT pins

The following boot modes are supported:

  • NAND Flash boot
    • 8-bit NAND
    • 16-bit NAND
  • NOR Flash boot
    • NOR Direct boot (8-bit or 16-bit)
    • NOR Legacy boot (8-bit or 16-bit)
    • NOR AIS boot (8-bit or 16-bit)
  • HPI Boot
  • I2C0 / I2C1 Boot
    • EEPROM (Master Mode)
    • External Host (Slave Mode)
  • SPI0 / SPI1 Boot
    • Serial Flash (Master Mode)
    • SERIAL EEPROM (Master Mode)
    • External Host (Slave Mode)
  • UART0 / UART1 / UART2 Boot
    • External Host

4.2 SYSCFG Module

The following system level features of the chip are controlled by the SYSCFG peripheral:

  • Readable Device, Die, and Chip Revision ID
  • Control of Pin Multiplexing
  • Priority of bus accesses different bus masters in the system
  • Capture at power on reset the chip BOOT[15:0] pin values and make them available to software
  • Special case settings for peripherals:
    • Locking of PLL controller settings
    • Default burst sizes for EDMA3 TC0 and TC1
    • Selection of the source for the eCAP module input capture (including on chip sources)
    • McASP AMUTEIN selection and clearing of AMUTE status for the three McASP peripherals
    • Control of the reference clock source and other side-band signals for both of the integrated USB PHYs
    • Clock source selection for EMIFA and EMIFB
  • Selects the source of emulation suspend signal (from either ARM or DSP) of peripherals supporting this function.
  • Control of on-chip inter-processor interrupts for signaling between ARM and DSP

Many registers are accessible only by a host (ARM or DSP) when it is operating in its privileged mode. (ex. from the kernel, but not from user space code).

Table 4-1 System Configuration (SYSCFG) Module Register Access

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION ACCESS
0x01C1 4000 REVID Revision Identification Register —
0x01C14008 DIEIDR0 Device Identification Register 0 —
0x01C1 400C DIEIDR1 Device Identification Register 1 —
0x01C1 4010 DIEIDR2 Device Identification Register 2 —
0x01C1 4014 DIEIDR3 Device Identification Register 3 —
0x01C1 4018 DEVIDR0 JTAG Identification Register —
0x01C1 4020 BOOTCFG Boot Configuration Register Privileged mode
0x01C1 4024 CHIPREVID Silicon Revision Identification Register Privileged mode
0x01C1 4038 KICK0R Kick 0 Register Privileged mode
0x01C1 403C KICK1R Kick 1 Register Privileged mode
0x01C1 4040 HOST0CFG Host 0 Configuration Register —
0x01C1 4044 HOST1CFG Host 1 Configuration Register —
0x01C1 40E0 IRAWSTAT Interrupt Raw Status/Set Register Privileged mode
0x01C1 40E4 IENSTAT Interrupt Enable Status/Clear Register Privileged mode
0x01C1 40E8 IENSET Interrupt Enable Register Privileged mode
0x01C1 40EC IENCLR Interrupt Enable Clear Register Privileged mode
0x01C1 40F0 EOI End of Interrupt Register Privileged mode
0x01C1 40F4 FLTADDRR Fault Address Register Privileged mode
0x01C1 40F8 FLTSTAT Fault Status Register —
0x01C1 4110 MSTPRI0 Master Priority 0 Register Privileged mode
0x01C1 4114 MSTPRI1 Master Priority 1 Register Privileged mode
0x01C1 4118 MSTPRI2 Master Priority 2 Register Privileged mode
0x01C1 4120 PINMUX0 Pin Multiplexing Control 0 Register Privileged mode
0x01C1 4124 PINMUX1 Pin Multiplexing Control 1 Register Privileged mode
0x01C1 4128 PINMUX2 Pin Multiplexing Control 2 Register Privileged mode
0x01C1 412C PINMUX3 Pin Multiplexing Control 3 Register Privileged mode
0x01C1 4130 PINMUX4 Pin Multiplexing Control 4 Register Privileged mode
0x01C1 4134 PINMUX5 Pin Multiplexing Control 5 Register Privileged mode
0x01C1 4138 PINMUX6 Pin Multiplexing Control 6 Register Privileged mode
0x01C1 413C PINMUX7 Pin Multiplexing Control 7 Register Privileged mode
0x01C1 4140 PINMUX8 Pin Multiplexing Control 8 Register Privileged mode
0x01C1 4144 PINMUX9 Pin Multiplexing Control 9 Register Privileged mode
0x01C1 4148 PINMUX10 Pin Multiplexing Control 10 Register Privileged mode
0x01C1 414C PINMUX11 Pin Multiplexing Control 11 Register Privileged mode
0x01C1 4150 PINMUX12 Pin Multiplexing Control 12 Register Privileged mode
0x01C1 4154 PINMUX13 Pin Multiplexing Control 13 Register Privileged mode
0x01C1 4158 PINMUX14 Pin Multiplexing Control 14 Register Privileged mode
0x01C1 415C PINMUX15 Pin Multiplexing Control 15 Register Privileged mode
0x01C1 4160 PINMUX16 Pin Multiplexing Control 16 Register Privileged mode
0x01C1 4164 PINMUX17 Pin Multiplexing Control 17 Register Privileged mode
0x01C1 4168 PINMUX18 Pin Multiplexing Control 18 Register Privileged mode
0x01C1 416C PINMUX19 Pin Multiplexing Control 19 Register Privileged mode
0x01C1 4170 SUSPSRC Suspend Source Register Privileged mode
0x01C1 4174 CHIPSIG Chip Signal Register —
0x01C1 4178 CHIPSIG_CLR Chip Signal Clear Register —
0x01C1 417C CFGCHIP0 Chip Configuration 0 Register Privileged mode
0x01C1 4180 CFGCHIP1 Chip Configuration 1 Register Privileged mode
0x01C1 4184 CFGCHIP2 Chip Configuration 2 Register Privileged mode
0x01C1 4188 CFGCHIP3 Chip Configuration 3 Register Privileged mode
0x01C1 418C CFGCHIP4 Chip Configuration 4 Register Privileged mode

4.3 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

  • Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state.
  • Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.

For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device boot and configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

  • Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors.
  • Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which, by definition, have margin to the VIL and VIH levels.
  • Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net.
  • For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).
  • Remember to include tolerances when selecting the resistor value.
  • For pullup resistors, also remember to include tolerances on the IO supply rail.
  • For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.
  • For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.
  • For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) for the device, see Section 4.6, Recommended Operating Conditions.
  • For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functions table.