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  • ONET2804TLP Low-Power, 28-Gbps, 4-Channel Limiting TIA

    • SBAS796 July   2017 ONET2804TLP

      PRODUCTION DATA.  

  • CONTENTS
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  • ONET2804TLP Low-Power, 28-Gbps, 4-Channel Limiting TIA
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 DC Electrical Characteristics
    5. 6.5 AC Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics: General
    8. 6.8 Typical Characteristics: Eye Diagrams
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Signal Path
      2. 7.3.2 Gain Adjustment
      3. 7.3.3 Amplitude Adjustment
      4. 7.3.4 Rate Select
      5. 7.3.5 Threshold Adjustment
      6. 7.3.6 Filter Circuitry
      7. 7.3.7 AGC and RSSI
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pad Control
      2. 7.4.2 Two-Wire Interface Control
    5. 7.5 Programming
      1. 7.5.1 Bus Idle
      2. 7.5.2 Start Data Transfer
      3. 7.5.3 Stop Data Transfer
      4. 7.5.4 Data Transfer
      5. 7.5.5 Acknowledge
    6. 7.6 Register Maps
      1. 7.6.1  Register Descriptions
      2. 7.6.2  Register 0: Control Settings (address = 00h) [reset = 0h]
      3. 7.6.3  Register 1: Amplitude and Rate for Channel 1 (address = 01h) [reset = 0h]
      4. 7.6.4  Register 2: Threshold and Gain for Channel 1 (address = 02h) [reset = 0h]
      5. 7.6.5  Register 7: Amplitude and Rate for Channel 2 (address = 07h) [reset = 0h]
      6. 7.6.6  Register 8: Threshold and Gain for Channel 1 (address = 08h) [reset = 0h]
      7. 7.6.7  Register 13: Amplitude and Rate for Channel 3 (address = 0Dh) [reset = 0h]
      8. 7.6.8  Register 14: Threshold and Gain for Channel 3 (address = 0Eh) [reset = 0h]
      9. 7.6.9  Register 19: Amplitude and Rate for Channel 4 (address = 13h) [reset = 0h]
      10. 7.6.10 Register 20: Threshold and Gain for Channel 4 (address = 14h) [reset = 0h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Pad Control Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Two-Wire Control Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • Y|0
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sbas796_oa
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DATA SHEET

ONET2804TLP Low-Power, 28-Gbps, 4-Channel Limiting TIA

1 Features

  • 4-Channel Multi-Rate Operation: Up to 28 Gbps
  • Dissipation at a 3-V Supply: 90 mW per Channel
  • Differential Transimpedance: 7.5 kΩ
  • Bandwidth: 17.5 GHz
  • Input-Referred Noise: 2 μArms
  • Input Overload Current: 3.2 mAPP
  • Programmable Output Voltage
  • Adjustable Gain and Bandwidth
  • Received Signal Strength Indicator (RSSI) for Each Channel
  • Isolation Between Channels (Die Only): 40 dB
  • Single Supply: 2.8 V to 3.3 V
  • Pad Control or 2-Wire Control
  • On-Chip Filter Capacitors
  • –40°C to +100°C Operation
  • Die Size: 3250 μm × 1450 μm, 750-μm Channel Pitch

2 Applications

  • 100 Gigabit Ethernet Optical Receivers
  • ITU OTL4.4
  • CFP2, CFP4, and QSFP28 Modules with Internal Retiming

3 Description

The ONET2804TLP device is a high-gain, limiting transimpedance amplifier (TIA) for parallel optical interconnects with data rates up to 28 Gbps. The device is used in conjunction with a 750-μm pitch photodiode array to convert an optical signal into a differential output voltage. An internal circuit provides the photodiode reverse bias voltage and senses the average photocurrent supplied to each photodiode.

The device can be used with pin control or a two-wire serial interface to allow control of the output amplitude, gain, bandwidth, and input threshold.

The ONET2804TLP provides 17.5-GHz bandwidth, a gain of 7.5 kΩ, an input-referred noise of 2 µArms, and a received signal strength indicator (RSSI) for each channel. 40-dB isolation between channels results in low crosstalk penalty in the receiver.

The device requires a single 2.8-V to 3.3-V supply and typically dissipates 90 mW per channel with a differential output amplitude of 300 mVPP. The device is characterized for operation from –40°C to +100°C and is available in die form with a 750-μm channel pitch.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ONET2804TLP Base Die in Waffle Pack 3250 µm × 1450 µm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

ONET2804TLP sbas796_first_page_simplified_schem.gif

Eye Diagram

ONET2804TLP D012_sbas796.png

4 Revision History

DATE REVISION NOTES
July 2017 * Initial release.

5 Pin Configuration and Functions

ONET2804TLP Bond Pad Assignment: Y Package
76-Pad Die
Top View
ONET2804TLP sbas796_padout.gif

Bond Pad Functions

PAD I/O DESCRIPTION
NAME NO.
ADR0 54 Digital input 2-wire interface address programming pin. Leave this pad open for a default address of 0001100. Grounding this pad changes the first address bit to a 1 (0001101).
ADR1 53 Digital input 2-wire interface address programming pin. Leave this pad open for a default address of 0001100. Grounding this pad changes the second address bit to a 1 (0001110).
AMPL 6 Digital input 3-state input for amplitude control of all four channels.
VCC: 500-mVPP differential output swing
Open: 300-mVPP differential output swing (default)
GND: 250-mVPP differential output swing
FILTER1 12, 14 Analog output FILTERx is the bias voltage for the photodiode cathode.
These pads are biased to VCC – 100 mV.
FILTER2 19, 21
FILTER3 26, 28
FILTER4 33, 35
GAIN 8 Digital input 3-state input for gain control of all four channels.
VCC: Minimum transimpedance
Open: Default transimpedance
GND: Medium transimpedance
GND 11, 15, 18, 22, 25, 29, 32, 36, 47, 48, 51, 52, 55, 56, 59, 60, 63, 64, 67, 68, 71, 72, 75, 76 Supply Circuit ground. All GND pads are connected on the die.
Bonding all pads is recommended, except for pads 11, 15, 18, 22, 25, 29, 32, and 36.
I2CENA 5 Digital input 2-wire control option. Leave the pad unconnected for pad control of the device.
Two-wire control can be enabled by applying a high signal to the pad.
IN1 13 Analog input INx is the data input to corresponding TIA channel (connect to photodiode anode)
IN2 20
IN3 27
IN4 34
NC 16, 17, 23, 24, 30, 31, 42, 61, 62, 69 No connection Do not connect
NRESET 70 Digital input Used to reset the 2-wire state machine and registers.
Leave open for normal operation and set low to reset the 2-wire interface.
OUT1– 73 Analog output Inverted CML data output for channel x. On-chip, 50-Ω, back-terminated to VCC.
OUT2– 65
OUT3– 57
OUT4– 49
OUT1+ 74 Analog output Noninverted CML data output for channel x. On-chip, 50-Ω, back-terminated to VCC.
OUT2+ 66
OUT3+ 58
OUT4+ 50
RATE 7 Digital input 3-state input for bandwidth control of all four channels.
VCC: Increase the bandwidth
Open: 21-GHz bandwidth (default)
GND: Reduce the bandwidth
RSSI1 9 Analog output Indicates the strength of the received signal (RSSI) for channel x if the photodiode is biased from FILTERx. The analog output current is proportional to the input data amplitude. Connect to an external resistor to ground (GND). For proper operation, ensure that the voltage at the RSSIx pad does not exceed VCC – 0.65 V. If the RSSI feature is not used, leave these pads open.
RSSI2 10
RSSI3 37
RSSI4 38
SCL 40 Digital input 2-wire interface serial clock input. Includes a 10-kΩ pullup resistor to VCC.
SDA 39 Digital input/output 2-wire interface serial data input. Includes a 10-kΩ pullup resistor to VCC.
TRSH 41 Digital input 3-state input for the threshold control.
VCC: Crossing point shifted down
Open: No threshold adjustment (default)
GND: Crossing point shifted up
VCCI1 4 Supply 2.8 V to 3.47 V supply voltage for the input TIAx stage.
VCCI2 3
VCCI3 44
VCCI4 43
VCCO1 1 Supply 2.8 V to 3.47 V supply voltage for the AGCx and CMLx amplifiers.
VCCO2 2
VCCO3 45
VCCO4 46

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage(1) VCCIx, VCCOx –0.3 4 V
Voltage(1) FILTERx, OUTx+, OUTx–, RSSIx, SCL, SDA, I2CENA, ICC_ADJ, AMPL, RATE, GAIN, TRSH, ADR1, ADR0, and NRESET –0.3 4 V
Average input current INx –0.7 5 mA
FILTERx –8 8 mA
Continuous current at outputs OUTx+, OUTx– –8 8 mA
Maximum junction temperature, TJ 125 °C
Storage temperature, Tstg –65 150 °C
(1) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins except INx ±1000 V
INx pins ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2.8 3.3 3.47 V
I(INx) Average input current 2.7 mA
TA Operating backside die temperature –40 100 °C
L(FILTER), L(IN) Wire-bond inductance at the FILTERx and INx pins 0.3 nH
C(PD) Photodiode capacitance 0.1 pF
VIH Digital input high voltage SDA, SCL 2 V
VIL Digital input low voltage SDA, SCL 0.8 V
3-state input high voltage VCC – 0.4 V
3-state input low voltage 0.4 V

6.4 DC Electrical Characteristics

over recommended operating conditions with VOD = 300 mVPP (unless otherwise noted); typical values are at VCC = 3.3 V and TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(3)
VCC Supply voltage 2.8 3.3 3.47 V A
ICC Supply current Per channel, 30-μAPP input, 27°C 22 42 mA A
Per channel, 30-μAPP input, maximum 85°C 30 C
Per channel, 30-μAPP input, maximum 100°C 36 C
P(RX) Receiver power dissipation Per channel, 30-μAPP input, 27°C 73 139 mW A
Per channel, 30-μAPP input, maximum 85°C 99 C
Per channel, 30-μAPP input, maximum 100°C 118 C
VIN Input bias voltage 0.75 0.85 0.98 V A
ROUT Output resistance Single-ended to VCC 40 50 60 Ω A
V(FILTER) Photodiode bias voltage(1) 2.8 3.2 V A
A(RSSI_IB) RSSI gain Resistive load to GND(2) 0.49 0.5 0.54 A/A A
RSSIx feature output offset current (no light) 0 2.5 µA A
(1) Regulated voltage is typically 100 mV lower than VCC.
(2) The RSSIx output is a current output that requires a resistive load to ground (GND). The voltage gain can be adjusted for the intended application by choosing the external resistor; however, for proper operation, ensure that the voltage at RSSIx does not exceed VCC – 0.65 V.
(3) Test levels: (A) 100% tested at 25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.

6.5 AC Electrical Characteristics

over recommended operating conditions with VOD = 300 mVPP (unless otherwise noted); typical values are at VCC = 3.3 V and TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(5)
Z21 Small-signal transimpedance 25-μAPP input signal 7.5 kΩ C
f(3dB-H) –3-dB bandwidth 25-μAPP input signal(1) 17.5 GHz C
f(3dB-L) Low-frequency, –3-dB bandwidth 30 kHz C
iN(IN) Input-referred RMS noise CPD = 0.1 pF, 28-GHz BT4 filter(2) 2 μA C
DJ Deterministic jitter 35 µAPP < iIN < 250 µAPP
(27.95 Gbps, PRBS9 pattern)		 2 psPP C
250 µAPP < iIN < 500 µAPP
(27.95 Gbps, PRBS9 pattern)		 2 C
500 µAPP < iIN < 2900 µAPP
(27.95 Gbps, PRBS9 pattern)		 4 C
VOD Differential output voltage 500-mVPP setting 250 500 700 mVPP C
Crosstalk Between adjacent channels, up to 20 GHz(3) –40 dB C
RSSIx response time 1 μs C
PSRR Power-supply rejection ratio f < 10 MHz(4) –15 dB C
(1) The small-signal bandwidth is specified over process corners, temperature, and supply voltage variation. The assumed photodiode capacitance is 0.1 pF and the bond-wire inductance is 0.3 nH. The small-signal bandwidth strongly depends on environmental parasitics. Careful attention to layout parasitics and external components is necessary to achieve optimal performance.
(2) Input-referred RMS noise is (RMS output noise) / (gain at 100 MHz).
(3) Die only, no wire bonds.
(4) PSRR is the differential output amplitude divided by the voltage ripple on the supply. No input current at INx.
(5) Test levels: (A) 100% tested at 25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information.

6.6 Timing Requirements

MIN NOM MAX UNIT
fSCK SCK clock frequency 400 kHz
tBUF Bus free time between START and STOP conditions 1.3 µs
tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated. 0.6 µs
tLOW Low period of the SCK clock 1.3 µs
tHIGH High period of the SCK clock 0.6 µs
tSUSTA Setup time for a repeated START condition 0.6 µs
tHDDAT Data hold time 0 µs
tSUDAT Data setup time 100 ns
tR Rise time of both SDA and SCK signals 300 ns
tF Fall time of both SDA and SCK signals 300 ns
tSUSTO Setup time for STOP condition 0.6 µs

6.7 Typical Characteristics: General

typical operating condition is at VCC = 3.3 V, TA = 25°C, and VOD = 300 mVPP (unless otherwise noted)
ONET2804TLP D001_sbas796.gif
Figure 1. Transimpedance vs Input Current
ONET2804TLP D003_sbas796.gif
Figure 3. Gain vs Frequency
(Test Fixture Loss De-Embedded)
ONET2804TLP D005_sbas796.gif
Figure 5. Differential Output Voltage vs Input Current
ONET2804TLP D007_sbas796.gif
Figure 7. Input-Referred Noise vs Ambient Temperature
ONET2804TLP D002_sbas796.gif
Figure 2. Small-Signal Transimpedance vs Ambient Temperature
ONET2804TLP D004_sbas796.gif
Figure 4. Small-Signal Bandwidth vs Ambient Temperature
(Test Fixture Loss De-Embedded)
ONET2804TLP D006_sbas796.gif
Figure 6. Deterministic Jitter vs Input Current
ONET2804TLP D009_sbas796.gif
Figure 8. RSSIx Output Current vs Average Input Current

6.8 Typical Characteristics: Eye Diagrams

typical operating condition is at VCC = 3.3 V, TA = 25°C, and VOD = 500 mVPP (unless otherwise noted)
ONET2804TLP D010_sbas796.png
27.95 Gbps
Figure 9. Output Eye-Diagram, 30-µAPP Input Current
ONET2804TLP D012_sbas796.png
27.95 Gbps
Figure 11. Output Eye-Diagram, 1.5-mAPP Input Current
ONET2804TLP D011_sbas796.png
27.95 Gbps
Figure 10. Output Eye-Diagram, 500-µAPP Input Current
ONET2804TLP D013_sbas796.png
27.95 Gbps
Figure 12. Output Eye-Diagram, 2.5-mAPP Input Current

 
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