SBOSAC7A february   2023  – july 2023 OPA1633

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Function
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Common-Mode Voltage
        1. 8.1.1.1 Resistor Matching
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PowerPAD™ Integrated Circuit Package Design Considerations
        2. 8.4.1.2 Power Dissipation and Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at VS = ±15 V, RF = 390 Ω, RL = 800 Ω, and G = +1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 0.2 2 mV
dVOS/dT Offset voltage drift ±0.6 μV/°C
PSRR Power supply rejection ratio 13 100 μV/V
INPUT BIAS CURRENT
IB Input bias current 6.8 11.5 μA
IOS Input offset current ±20 ±400 nA
NOISE
eN Input voltage noise density f = 10 kHz 1.1 nV/√Hz
iN Input current noise density f = 10 kHz 1.3 pA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage (V−) + 1.5 (V+) − 1
CMRR Common-mode rejection ratio 80 100 dB
INPUT IMPEDANCE
Input impedance Common-mode Measured into each input pin 320 || 1.3 MΩ || pF
Differential Measured into each input pin 12 || 2.3 kΩ || pF
OPEN-LOOP GAIN
AOL Open-loop gain 91 97 dB
FREQUENCY RESPONSE
SSBW Small signal bandwidth G = +1, RF= 348 Ω 200 MHz
(VO = 100 mVPP, peaking < 0.5 dB) G = +2, RF = 602 Ω 117
G = +5, RF = 1.5 kΩ 53
G = +10, RF = 3.01 kΩ 26
Bandwidth for 0.1-dB flatness G = +1, VO = 100 mVPP 40 MHz
Peaking at a gain of 1 VO = 100 mVPP 0.25 dB
LSBW Large-signal bandwidth G = +2, VO = 20 VPP 3 MHz
SR Slew rate  (25% to 75%) G = +1 80 V/μs
Rise and fall time G = +1, VO = 5-V step
 62 ns
ts Settling time To 0.1% G = +1, VO = 2-V step 30 ns
To 0.01% G = +1, VO = 2-V step 40
THD+N Total harmonic distortion + noise Differential input/output G = +1, f = 1 kHz, 
VO = 3 VRMS		 RL = 600 Ω 131 dB
RL = 2 kΩ 132
Single-ended in/differential out G = +1, f = 1 kHz, 
VO = 3 VRMS		 RL = 600 Ω 131
RL = 2 kΩ 132
IMD Intermodulation distortion Differential input/output G = +1, SMPTE/DIN, VO = 2 VPP RL = 600 Ω 125 dB
RL = 2 kΩ 125
Single-ended in/differential out G = +1, SMPTE/DIN, VO = 2 VPP RL = 600 Ω 125
RL = 2 kΩ 125
Headroom THD < 0.01%, RL = 2 kΩ 40 VPP
OUTPUT
VO Voltage output swing RL = 1 kΩ (V+) − 1.9 (V−) + 1.9 V
IO Output current 65 85 mA
Closed-loop output impedance G = +1, f = 100 kHz 0.1 Ω
POWER DOWN
Enable voltage threshold (V−) + 1.45 (V−) + 1.5 V
Disable voltage threshold (V−) + 0.8 (V−) + 1.4 V
ISD Shutdown current VS = ±5 V, VEnable = −5 V 0.77 mA
VS = ±15 V, VEnable = −15 V 1.4
Turn-on delay Time for IQ to reach 50% 0.12 μs
Turn-off delay Time for IQ to reach 50% 0.03 μs
POWER SUPPLY
IQ Quiescent current 11 13.2 mA