SBOSA00B December   2019  – August 2020 OPA1637

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Characterization Configuration
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Super-Beta Input Bipolar Transistors
      2. 8.3.2 Power Down
      3. 8.3.3 Flexible Gain Setting
      4. 8.3.4 Amplifier Overload Power Limit
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving Capacitive Loads
      2. 9.1.2 Operating the Power-Down Feature
      3. 9.1.3 I/O Headroom Considerations
      4. 9.1.4 Noise Performance
    2. 9.2 Typical Applications
      1. 9.2.1 Current-Output Audio DAC Buffer to Class-D Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 An MFB Filter Driving an ADC Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Differential Microphone Input to Line Level
        1. 9.2.3.1 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Driving Capacitive Loads

The capacitive load of an ADC, or some other next-stage device, is commonly required to be driven. Directly connecting a capacitive load to the output pins of a closed-loop amplifier such as the OPA1637 can lead to an unstable response. One typical remedy to this instability is to add two small series resistors (RISO) at the outputs of the OPA1637 before the capacitive load. Good practice is to leave a place for the RISO elements in a board layout (a 0-Ω value initially) for later adjustment, in case the response appears unacceptable.

For applications where the OPA1637 is used as an output device to drive an unknown capacitive load, such as a cable, RISO is required. Figure 9-1 shows the required RISO value for a 40-degree phase-margin response. The peak required RISO value occurs when CL is between 500 pF and 1 nF. As CL increases beyond 1 nF, the bandwidth response of the device reduces, resulting in a slower response but no major degradation in phase margin. For a typical cable type, such as Belden 8451, capacitive loading can vary from 340 pF (10-foot cable) to 1.7 nF (50-foot cable). Selecting RISO to be 100 Ω provides sufficient phase margin regardless of the cable length. RISO can also be used within the loop feedback of the amplifier; however, simulation must be used to verify the stability of the system.

GUID-B5B4344A-9E2E-4152-985D-0665CDB9C0FB-low.gifFigure 9-1 Required Isolation Resistance vs Capacitive Load for a 40° Phase Margin