SBOSA00B December   2019  – August 2020 OPA1637

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Characterization Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Super-Beta Input Bipolar Transistors
      2. 8.3.2 Power Down
      3. 8.3.3 Flexible Gain Setting
      4. 8.3.4 Amplifier Overload Power Limit
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving Capacitive Loads
      2. 9.1.2 Operating the Power-Down Feature
      3. 9.1.3 I/O Headroom Considerations
      4. 9.1.4 Noise Performance
    2. 9.2 Typical Applications
      1. 9.2.1 Current-Output Audio DAC Buffer to Class-D Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 An MFB Filter Driving an ADC Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Differential Microphone Input to Line Level
        1. 9.2.3.1 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1.2 Detailed Design Procedure

This design provides current-to-voltage conversion from a current-output audio DAC into a voltage-input, class-D amplifier. The order of design priorities are as follows:

  • Select feedback-resistor values based on the gain required from the current-output stage to the voltage-input stage. For this design, the full-scale, peak-to-peak output current of the PCM1795 ( IOUTL/R+ – IOUTL/R–) is ±4 mA. A gain of 1k gives a wide voltage swing of ±4 V, allowing for high SNR without exceeding the input voltage limit of the TPA3251.
  • After the gain is fixed, select the output common-mode voltage. The output common-mode voltage determines the input common-mode voltage in this configuration. To set the nominal output voltage of the PCM1795 to 0 V (which corresponds to the input common mode voltage of the OPA1637), shift the output negatively from the desired common-mode input voltage by the gain multiplied by the dc center current value of the PCM1795 (3.5 mA). In this case, –3.5 V satisfies the design goal.
  • A bypass capacitor from the VOCM pin to ground must be selected to filter noise from the voltage divider. The capacitor selection is determined by balancing the startup time of the system with the output common-mode noise. A higher capacitance gives a lower frequency filter cutoff on the VOCM pin, thus giving lower noise performance, but also slows down the initial startup time of the circuit as a result of the RC delay from the resistor divider in combination with the filter capacitor.
  • Select CF so that the desired bandwidth of the active filter is achieved. The 3-dB frequency is determined by the reciprocal of the product of RF and CF.
  • Use a passive filter on the output to increase noise filtering beyond the desired bandwidth. The passive filter formed by RD1,2 and CDF adds an additional real pole to the filter response. If the pole is designed at the same frequency as the active filter pole, the overall 3-dB frequency shifts to a lower frequency value, and the step response is overdamped. A trade-off must be made to give optimal transient response versus increased filter attenuation at higher frequencies. For this design, the second pole is set to 106 kHz.