SBOS556D
June 2011 – August 2020
OPA171-Q1
,
OPA2171-Q1
,
OPA4171-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
Pin Functions : OPA171-Q1 and OPA2171-Q1
Pin Functions : OPA4171-Q1
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information — OPA171-Q1 and OPA2171-Q1
6.5
Thermal Information — OPA4171-Q1
6.6
Electrical Characteristics
6.7
Typical Characteristics
6.7.1
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Operating Characteristics
7.3.2
Phase-Reversal Protection
7.3.3
Capacitive Load and Stability
7.4
Device Functional Modes
7.4.1
Common-Mode Voltage Range
8
Application and Implementation
8.1
Application Information
8.1.1
Electrical Overstress
8.2
Typical Application
8.2.1
Capacitive Load Drive Solution Using an Isolation Resistor
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curve
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Related Links
11.3
Receiving Notification of Documentation Updates
11.4
Support Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DBV|5
MPDS018T
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sbos556d_oa
sbos556d_pm
6.7.1
Typical Characteristics
Figure 6-1
Offset Voltage Production Distribution
Figure 6-3
Offset Voltage vs Temperature
Figure 6-5
Offset Voltage vs Common-Mode Voltage: V
SUPPLY
(V) = ±18 V
(Upper Stage)
Figure 6-7
I
B
and I
OS
vs Common-Mode Voltage
Figure 6-9
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 6-11
CMRR vs Temperature
Figure 6-13
0.1- to 10-Hz Noise
Figure 6-15
THD+N Ratio vs Frequency
Figure 6-17
Quiescent Current vs Temperature
Figure 6-19
Open-Loop Gain and Phase vs Frequency
Figure 6-21
Open-Loop Gain vs Temperature
Figure 6-23
Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 6-25
No Phase Reversal
Figure 6-27
Negative Overload Recovery
Figure 6-29
Small-Signal Step Response (100 mV)
G = –1
R
L
= 10 kΩ
C
L
= 100 pF
Figure 6-31
Large-Signal Step Response
G = –1
Figure 6-33
Large-Signal Settling Time (10-V Negative Step)
Figure 6-35
Maximum Output Voltage vs Frequency
Figure 6-2
Offset Voltage Drift Distribution
Figure 6-4
Offset Voltage vs Common-Mode Voltage: V
SUPPLY
(V) = ±18 V
Figure 6-6
Offset Voltage vs Power Supply
Figure 6-8
Input Bias Current vs Temperature
Figure 6-10
CMRR and PSRR vs Frequency
(Referred-to Input)
Figure 6-12
PSRR vs Temperature
Figure 6-14
Input Voltage Noise Spectral Density vs Frequency
Figure 6-16
THD+N vs Output Amplitude
Figure 6-18
Quiescent Current vs Supply Voltage
Figure 6-20
Closed-Loop Gain vs Frequency
Figure 6-22
Open-Loop Output Impedance vs Frequency
Figure 6-24
Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 6-26
Positive Overload Recovery
Figure 6-28
Small-Signal Step Response (100 mV)
G = 1
R
L
= 10 kΩ
C
L
= 100 pF
Figure 6-30
Large-Signal Step Response
G = –1
Figure 6-32
Large-Signal Settling Time (10-V Positive Step)
Figure 6-34
Short-Circuit Current vs Temperature
Figure 6-36
Channel Separation vs Frequency