SBOS618I December   2013  – May 2018 OPA172 , OPA2172 , OPA4172

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      JFET-Input Low-Noise Amplifier
      2.      Superior THD Performance
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Device Comparison
    2. 5.2 Device Family Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: OPA172
    2.     Pin Functions: OPA2172 and OPA4172
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA172
    5. 7.5 Thermal Information: OPA2172
    6. 7.6 Thermal Information: OPA4172
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics: Table of Graphs
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 EMI Rejection
      2. 8.3.2 Phase-Reversal Protection
      3. 8.3.3 Capacitive Load and Stability
    4. 8.4 Device Functional Modes
      1. 8.4.1 Common-Mode Voltage Range
      2. 8.4.2 Electrical Overstress
      3. 8.4.3 Overload Recovery
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Bidirectional Current Source
      3. 9.2.3 JFET-Input Low-Noise Amplifier
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 TINA-TI (Free Software Download)
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DCK Package: OPA172
SC70-5
Top View
OPA172 OPA2172 OPA4172 po_sc70_bos406.gif
DBV Package: OPA172
SOT-23-5
Top View
OPA172 OPA2172 OPA4172 po_sot23-5_bos516.gif
D Package: OPA172
SOIC-8
Top View
OPA172 OPA2172 OPA4172 po_so-8_bos516.gif
1. No internal connection.

Pin Functions: OPA172

PIN I/O DESCRIPTION
NAME OPA172
D (SOIC) DBV (SOT) DCK (SC70)
+IN 3 3 1 I Noninverting input
–IN 2 4 3 I Inverting input
NC 1, 5, 8 — — — No internal connection
OUT 6 1 4 O Output
V+ 7 5 5 — Positive (highest) power supply
V– 4 2 2 — Negative (lowest) power supply
D and DGK Packages: OPA2172
SOIC-8 and VSSOP-8
Top View
OPA172 OPA2172 OPA4172 po_vssop-8_bos516.gif
DRG Package: OPA2172
WSON-8
Top View
OPA172 OPA2172 OPA4172 po_drg_opa1688_sbos724.gif
D and PW Packages: OPA4172
SO-14 and TSSOP-14
Top View
OPA172 OPA2172 OPA4172 po_so-14_bos516.gif

Pin Functions: OPA2172 and OPA4172

PIN I/O DESCRIPTION
NAME OPA2172 OPA4172
D (SOIC),
DGK (VSSOP)		 DRG (WSON) D (SOIC),
PW (TSSOP)
+IN A 3 1 3 I Noninverting input, channel A
+IN B 5 4 5 I Noninverting input, channel B
+IN C — — 10 I Noninverting input, channel C
+IN D — — 12 I Noninverting input, channel D
–IN A 2 8 2 I Inverting input, channel A
–IN B 6 5 6 I Inverting input, channel B
–IN C — — 9 I Inverting input,,channel C
–IN D — — 13 I Inverting input, channel D
OUT A 1 7 1 O Output, channel A
OUT B 7 6 7 O Output, channel B
OUT C — — 8 O Output, channel C
OUT D — — 14 O Output, channel D
V+ 8 2 4 — Positive (highest) power supply
V– 4 3 11 — Negative (lowest) power supply