SBOS618I
December 2013 – May 2018
OPA172
,
OPA2172
,
OPA4172
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
JFET-Input Low-Noise Amplifier
Superior THD Performance
4
Revision History
5
Device Comparison
5.1
Device Comparison
5.2
Device Family Comparison
6
Pin Configuration and Functions
Pin Functions: OPA172
Pin Functions: OPA2172 and OPA4172
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information: OPA172
7.5
Thermal Information: OPA2172
7.6
Thermal Information: OPA4172
7.7
Electrical Characteristics
7.8
Typical Characteristics: Table of Graphs
7.9
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
EMI Rejection
8.3.2
Phase-Reversal Protection
8.3.3
Capacitive Load and Stability
8.4
Device Functional Modes
8.4.1
Common-Mode Voltage Range
8.4.2
Electrical Overstress
8.4.3
Overload Recovery
9
Applications and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Capacitive Load Drive Solution Using an Isolation Resistor
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curve
9.2.2
Bidirectional Current Source
9.2.3
JFET-Input Low-Noise Amplifier
10
Power-Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Development Support
12.1.1.1
TINA-TI (Free Software Download)
12.2
Documentation Support
12.2.1
Related Documentation
12.3
Related Links
12.4
Community Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
D|8
MSOI002K
DCK|5
MPDS025J
DBV|5
MPDS018T
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sbos618i_oa
sbos618i_pm
7.9
Typical Characteristics
At V
S
= ±18 V, V
CM
= V
S
/ 2, R
LOAD
= 10 kΩ connected to V
S
/ 2, and C
L
= 100 pF, unless otherwise noted.
Figure 1.
Offset Voltage Production Distribution
Figure 3.
Offset Voltage vs Temperature
(V
S
= ±18 V)
Figure 5.
Offset Voltage vs Common-Mode Voltage
(Upper Stage)
Figure 7.
Input Bias Current vs Common-Mode Voltage
Figure 9.
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 11.
CMRR vs Temperature
Figure 13.
0.1-Hz to 10-Hz Noise
Figure 15.
THD+N Ratio vs Frequency
Figure 17.
Quiescent Current vs Temperature
Figure 19.
Open-Loop Gain and Phase vs Frequency
Figure 21.
Open-Loop Gain vs Temperature
Figure 23.
Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 25.
Positive Overload Recovery
Figure 27.
Negative Overload Recovery
Figure 29.
Small-Signal Step Response (10 mV, G = –1)
Figure 31.
Small-Signal Step Response (100 mV, G = –1)
Figure 33.
Large-Signal Step Response (10 V, G = –1)
Figure 35.
Large-Signal Settling Time (10-V Positive Step)
Figure 37.
No Phase Reversal
Figure 39.
Maximum Output Voltage vs Frequency
Figure 41.
Channel Separation vs Frequency
Figure 2.
Offset Voltage Drift Production Distribution
Figure 4.
Offset Voltage vs Common-Mode Voltage
(V
S
= ±18 V)
Figure 6.
Offset Voltage vs Power Supply
Figure 8.
Input Bias Current vs Temperature
Figure 10.
CMRR and PSRR vs Frequency
(Referred-To-Input)
Figure 12.
PSRR vs Temperature
Figure 14.
Input Voltage Noise Spectral Density vs Frequency
Figure 16.
THD+N vs Output Amplitude
Figure 18.
Quiescent Current vs Supply Voltage
Figure 20.
Closed-Loop Gain vs Frequency
Figure 22.
Open-Loop Output Impedance vs Frequency
Figure 24.
Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 26.
Positive Overload Recovery (Zoomed In)
Figure 28.
Negative Overload Recovery (Zoomed In)
Figure 30.
Small-Signal Step Response (10 mV, G = +1)
Figure 32.
Small-Signal Step Response (100 mV, G = +1)
Figure 34.
Large-Signal Step Response (10 V, G = +1)
Figure 36.
Large-Signal Settling Time (10-V Negative Step)
Figure 38.
Short-Circuit Current vs Temperature
Figure 40.
EMIRR vs Frequency