OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp with e-trim

1 Features

• Low Offset Voltage: ±5 µV
• Low Offset Voltage Drift: ±0.2 µV/°C
• Low Noise: 5.5 nV/√Hz at 1 kHz
• High Common-Mode Rejection: 140 dB
• Low Bias Current: ±5 pA
• Rail-to-Rail Input and Output
• Wide Bandwidth: 10 MHz GBW
• High Slew Rate: 20 V/µs
• Low Quiescent Current: 1 mA per Amplifier
• Wide Supply: ±2.25 V to ±18 V, 4.5 V to 36 V
• EMI/RFI Filtered Inputs
• Differential Input Voltage Range to Supply Rail
• High Capacitive Load Drive Capability: 1 nF
• Industry Standard Packages:
  • Single in SOIC-8, SOT-23-5, and VSSOP-8
  • Dual in SOIC-8 and VSSOP-8
  • Quad in SOIC-14 and TSSOP-14

2 Applications

• Multiplexed Data-Acquisition Systems
• Test and Measurement Equipment
• High-Resolution ADC Driver Amplifiers
• SAR ADC Reference Buffers
• Programmable Logic Controllers
• High-Side and Low-Side Current Sensing
• High Precision Comparator

3 Description

The OPAx192 family (OPA192, OPA2192, and OPA4192) is a new generation of 36-V, e-trim operational amplifiers.

These devices offer outstanding dc precision and ac performance, including rail-to-rail input/output, low offset (±5 µV, typ), low offset drift (±0.2 µV/°C, typ), and 10-MHz bandwidth.

Unique features such as differential input-voltage range to the supply rail, high output current (±65 mA), high capacitive load drive of up to 1 nF, and high slew rate (20 V/µs) make the OPA192 a robust, high-performance operational amplifier for high-voltage industrial applications.

The OPA192 family of op amps is available in standard packages and is specified from –40°C to +125°C.

1. For all available packages, see the package option addendum at the end of the data sheet.

OPA192 in a High-Voltage, Multiplexed, Data-Acquisition System

4 Revision History

Changes from D Revision (September 2015) to E Revision

• Changed PW package from product preview to production dataGo
• Added PW package to test condition for input offset voltage driftGo
• Added PW package to test condition for input offset voltage driftGo
• Added PW package condition to Figure 8 Go
• Added PW package condition to Figure 10 Go
• Added PW package condition to Figure 52 Go
• Changed Figure 70 to fix typosGo

Changes from C Revision (March 2015) to D Revision

• Changed device status to Production Data; OPA4192 released to Production Go
• Deleted footnote 2 from Device Information table Go
• Deleted footnote 2 from Pin Configuration and Functions sectionGo
• Changed ESD Ratings table: added correct OPA4192 CDM specifications Go
• Added Frequency Response, Crosstalk parameter to Electrical Characteristics: V_S = ±4 V to ±18 V table Go
• Added Frequency Response, Crosstalk parameter to Electrical Characteristics: V_S = ±2.25 V to ±4 V table Go
• Changed Typical Characteristics to current standards (split curves and table of graphs into separate sections to be SDS compliant) Go
• Added Crosstalk vs Frequency row to Table 1 Go
• Added Figure 48 Go

Changes from B Revision (March 2014) to C Revision

• Added CDM row for OPA2192, OPA4192 in ESD Ratings tableGo
• Changed input offset voltage values for V_CM ≥ (V+) – 1.5 V test conditionGo
• Changed Input offset voltage parameter typical specs for V_CM = (V+) – 1.5 V test conditions Go
• Changed test conditions for dV_OS/dT parameterGo
• Changed input offset voltage max values and test conditions for V_CM = (V+) – 3 V test conditionGo
• Changed input offset voltage values and test conditions for V_CM = (V+) – 1.5 V test conditionGo
• Changed Input offset voltage parameter typical specs for V_CM = (V+) – 1.5 V test conditionsGo
• Changed test conditions for dV_OS/dT parameter Go
• Added text to last bullet of Layout Guidelines sectionGo

Changes from A Revision (January 2014) to B Revision

• Added ESD Ratings and Recommended Operating Conditions tables, and Parameter Measurement Information, Application and Implementation, Power-Supply Recommendations, and Device and Documentation Support sections, and moved existing sectionsGo
• Changed all OPA192 and OPA2192 packages to production data.Go
• Changed package names to latest standard; changed all MSOP to VSSOP, SO to SOIC, and SOT23 to SOT Go
• Deleted DCK package pin configurationGo
• Added thermal information for OPA192 DBV and DGK packagesGo
• Added OPA2192 and OPA4192 Thermal Information tables Go
• Added rows with additional test conditions to input offset voltage parameterGo
• Changed Input offset voltage drift parameter Go
• Changed CMRR test conditions Go
• Added rows with additional test conditions to input offset voltage parameterGo
• Changed Input offset voltage drift parameterGo
• Changed PSSR parameter Go
• Changed CMRR test conditions Go
• Added Output sectionGo
• Added typical characteristic curves to Table 1 Go
• Added T_A = 25°C to Typical Characteristics condition line Go
• Added nine new histogram plots from Figure 2 to Figure 10Go
• Changed Figure 11 to show more unitsGo
• Changed Figure 19 Go
• Added text to Application Information sectionGo
• Changed text in Layout Guidelines sectionGo

Changes from * Revision (December 2013) to A Revision

• Changed first paragraph of 16-Bit Precision Multiplexed Data-Acquisition System sectionGo
• Changed Figure 66 and titleGo
• Changed TIDU181 reference design titleGo

5 Pin Configuration and Functions

DBV Package: OPA192

5-Pin SOT

Top View

D and DGK Packages: OPA192

8-Pin SOIC and VSSOP

Top View

D and DGK Packages: OPA2192

8-Pin SOIC and VSSOP

Top View

D and PW Packages: OPA4192

14-Pin SOIC and TSSOP

Top View

6 Specifications

6.10 Typical Characteristics

At T_A = 25°C, V_S = ±18 V, V_CM = V_S / 2, R_LOAD = 10 kΩ connected to V_S / 2, and C_L = 100 pF, unless otherwise noted.

Figure 1. Offset Voltage Production Distribution at 25°C

Figure 3. Offset Voltage Production Distribution at 85°C

Figure 5. Offset Voltage Production Distribution at –25°C

OPA192ID and OPA2192ID

Figure 7. Offset Voltage Drift Distribution
from –40°C to +125°C

OPA192ID and OPA2192ID

Figure 9. Offset Voltage Drift Distribution
from 0°C to 85°C

Figure 11. Offset Voltage vs Temperature

Figure 13. Offset Voltage vs Common-Mode Voltage

Figure 15. Offset Voltage vs Power Supply

Figure 17. Closed-Loop Gain and Phase vs Frequency

Figure 19. Input Bias Current vs Temperature

Figure 21. CMRR and PSRR vs Frequency

Figure 23. PSRR vs Temperature

Figure 25. Input Voltage Noise Spectral Density
vs Frequency

Figure 27. THD+N vs Output Amplitude

Figure 29. Quiescent Current vs Temperature

Figure 31. Open-Loop Output Impedance vs Frequency

Figure 33. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)

Figure 35. Positive Overload Recovery

Figure 37. Small-Signal Step Response (100 mV)

Figure 39. Large-Signal Step Response

Figure 41. Settling Time (5-V Positive Step)

Figure 43. Settling Time (5-V Negative Step)

Figure 45. Maximum Output Voltage vs Frequency

Figure 47. Propagation Delay Falling Edge

Figure 2. Offset Voltage Production Distribution at 125°C

Figure 4. Offset Voltage Production Distribution at 0°C

Figure 6. Offset Voltage Production Distribution at –40°C

OPA192IDBV, OPA192IDGK, OPA2192IDGK, and OPA4192IPW

Figure 8. Offset Voltage Drift Distribution
from –40°C to +125°C

OPA192IDBV, OPA192IDGK, OPA2192IDGK, and OPA4192IPW

Figure 10. Offset Voltage Drift Distribution
from 0°C to 85°C

Figure 12. Offset Voltage vs Common-Mode Voltage

Figure 14. Offset Voltage vs Common-Mode Voltage

Figure 16. Open-Loop Gain and Phase vs Frequency

Figure 18. Input Bias Current vs Common-Mode Voltage

Figure 20. Output Voltage Swing vs Output Current (Maximum Supply)

Figure 22. CMRR vs Temperature

Figure 24. 0.1-Hz to 10-Hz Noise

Figure 26. THD+N Ratio vs Frequency

Figure 28. Quiescent Current vs Supply Voltage

Figure 30. Open-Loop Gain vs Temperature

Figure 32. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)

Figure 34. No Phase Reversal

Figure 36. Negative Overload Recovery

Figure 38. Small-Signal Step Response (100 mV)

Figure 40. Settling Time (10-V Positive Step)

Figure 42. Settling Time (10-V Negative Step)

Figure 44. Short-Circuit Current vs Temperature

Figure 46. Propagation Delay Rising Edge

Figure 48. Crosstalk vs Frequency

7 Parameter Measurement Information

7.1 Input Offset Voltage Drift

The OPAx192 family of operational amplifiers is manufactured using TI’s e-trim technology. Each amplifier input offset voltage and input offset voltage drift is trimmed in production, thereby minimizing errors associated with input offset voltage and input offset voltage drift. The e-trim technology is a TI proprietary method of trimming internal device parameters during either wafer probing or final testing. When trimming input offset voltage drift the systematic or linear drift error on each device is trimmed to zero. This results in the remaining errors associated with input offset drift are minimal and are the result from only nonlinear error sources. Figure 49 illustrates this concept.

Figure 49. Input Offset Before and After Drift Trim

A common method of specifying input offset voltage drift is the box method. The box method estimates a maximum input offset drift by bounding the offset voltage versus temperature curve with a box and using the corners of this bounding box to determine the drift. The slope of the line connecting the diagonal corners of the box corresponds to the input offset voltage drift. Figure 50 shows the box method concept. The box method works particularly well when the input offset drift is dominated by the linear component of drift, but because the OPA192 family uses TI’s e-trim technology to remove the linear component input offset voltage drift, the box method is not a particularly useful method of accurately performing an error analysis. Figure 50 shows 30 typical units of the OPAx192 with the box method superimposed for illustrative purposes. The boundaries of the box are determined by the specified temperature range along the x-axis and the maximum specified input offset voltage across that same temperature range along the y-axis. Using the box method predicts an input offset voltage drift of 0.9 µV/°C. As shown in Figure 50, the slopes of the actual input offset voltage versus temperature are much less than that predicted by the box method. The box method predicts a pessimistic value for the maximum input offset voltage drift and is not recommended when performing an error analysis.

Figure 50. The Box Method

Instead of the box method, a convenient way to illustrate input offset drift is to compute the slopes of the input offset voltage versus temperature curve. This is the same as computing the input offset drift at each point along the input offset voltage versus temperature curve. The results for the OPAx192 family are shown in Figure 51 and Figure 52.

Figure 51. Input Offset Voltage Drift vs Temperature
(OPA192ID and OPA2192ID)

Figure 52. Input Offset Voltage Drift vs Temperature
(OPA192IDBV, OPA192IDGK, OPA2192IDGK, and OPA4192IPW)

As shown in Figure 51, the input offset drift is typically less than ±0.3 µV/°C over the range from –40°C to +125°C. When performing an error analysis over the full specified temperature range, use the typical and maximum values for input offset voltage drift as described in the Electrical Characteristics tables. If a reduced temperature range is applicable, use the information shown in Figure 51 or Figure 52 when performing an error analysis. To determine the change in input offset voltage, use Equation 1:

Equation 1. ΔV_OS = ΔT × dV_OS/dT

where

• ΔV_OS = Change in input offset voltage
• ΔT = Change in temperature
• dV_OS/dT = Input offset voltage drift

For example, determine the amount of OPA192ID input offset voltage change over the temperature range of 25°C to 75°C for 1 σ (68%) of the units. As shown in Figure 51, the input offset drift is typically 0.15 µV/°C. This input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.15 µV/°C = 7.5 µV .

For 3 σ (99.7%) of the units, Figure 51 shows a typical input offset drift of 0.4 µV/°C. This input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.4 µV/°C = 20 µV.

Figure 53 shows six typical units.

Figure 53. Input Offset Voltage Drift vs Temperature for Six Typical Units