The OPA210 and OPA2210 (OPAx210) are the next generation of OPAx209 operational amplifier (op amp). The OPAx210 precision op amps are built on TI's precision, super-beta, complementary bipolar semiconductor process, which offers ultra-low flicker noise, low offset voltage, and low offset voltage temperature drift.
The OPAx210 achieve very low voltage noise density (2.2 nV/√Hz) while consuming only 2.5 mA (maximum) per amplifier. These devices also offer rail-to-rail output swing, which helps maximize dynamic range.
In precision data-acquisition applications, the OPAx210 provide fast settling time to 16-bit accuracy, even for 10-V output swings. Excellent ac performance, combined with only 35 μV (maximum) of offset and 0.6 µV/°C (maximum) drift over temperature, makes the OPAx210 an excellent choice for high-speed, high-precision applications.
The OPAx210 are specified over a wide dual power-supply range of ±2.25 V to ±18 V, or single-supply operation from 4.5 V to 36 V, are specified from –40°C to +125°C.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
OPA210 | SOIC (8) | 2.90 mm × 1.60 mm |
SOT-23 (5) | 2.90 mm × 1.60 mm | |
VSSOP (8) | 3.00 mm × 3.00 mm | |
OPA2210 | SOIC (8) | 4.90 mm × 3.91 mm |
VSSOP (8) | 3.00 mm × 3.00 mm | |
WSON (8) | 3.00 mm × 3.00 mm |
Changes from Revision G (April 2021) to Revision H (August 2021)
Changes from Revision F (January 2021) to Revision G (April 2021)
Changes from Revision E (Novembver 2020) to Revision F (January 2021)
Changes from Revision D (January 2020) to Revision E (November 2020)
Changes from Revision C (September 2019) to Revision D (January 2020)
Changes from Revision B (March 2019) to Revision C (September 2019)
Changes from Revision A (December 2018) to Revision B (February 2019)
Changes from Revision * (September 2018) to Revision A (December 2018)
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOIC, VSSOP | SOT-23 | ||
–IN | 2 | 4 | I | Inverting input |
+IN | 3 | 3 | I | Noninverting input |
NC | 1, 5, 8 | — | — | No internal connection |
OUT | 6 | 1 | O | Output |
V– | 4 | 2 | — | Negative (lowest) power supply |
V+ | 7 | 5 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
–IN A | 2 | I | Inverting input, channel A |
+IN A | 3 | I | Noninverting input, channel A |
–IN B | 6 | I | Inverting input, channel B |
+IN B | 5 | I | Noninverting input, channel B |
OUT A | 1 | O | Output, channel A |
OUT B | 7 | O | Output, channel B |
V– | 4 | — | Negative (lowest) power supply |
V+ | 8 | — | Positive (highest) power supply |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Voltage | Supply voltage, VS = (V+) – (V–) | 40 | V | ||
Signal input pins(2) | (V–) – 0.5 | (V+) + 0.5 | |||
Signal input pins | Differential | 1 | |||
Current | Signal input pins(2) | –10 | 10 | mA | |
Output short circuit(3) | Continuous | ||||
Temperature | Junction, TJ | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | MAX | UNIT | |
---|---|---|---|
Specified voltage, VS | ±2.25 | ±18 | V |
Specified temperature | –40 | 125 | °C |
Operating temperature, TA | –55 | 150 | °C |
THERMAL METRIC(1) | OPA210 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | DGK (VSSOP) | DBV (SOT-23) | |||
8 PINS | 8 PINS | 5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 131.2 | 171.3 | 180.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 71.6 | 64.7 | 67.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 74.6 | 92.4 | 102.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 22.4 | 10.4 | 10.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 73.8 | 90.9 | 100.3 | °C/W |
RθJC(bottom) | Junction-to-case (bottom) thermal resistance | N/A | N/A | N/A | °C/W |
THERMAL METRIC(1) | OPA2210 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | DGK (VSSOP) | DRG (SON) | |||
8 PINS | 8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 126.1 | 132.7 | 52.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 65.7 | 38.5 | 51.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 69.5 | 52.1 | 24.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 17.4 | 2.4 | 1.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 68.9 | 52.8 | 24.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | n/a | 9.0 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | |||||||
VOS | Input offset voltage | VS = ±15 V, VCM = 0 V | ±5 | ±35 | µV | ||
dVOS/dT | Input offset voltage drift | TA = –40°C to 125°C | ±0.1 | ±0.5 | µV/°C | ||
VOS -matching | Input offset voltage matching | ±5 | ±35 | µV | |||
PSRR | vs power supply | VS = ±2.25 V to ±18 V | TA = 25°C | 0.05 | 0.5 | µV/V | |
TA = –40°C to 125°C | ±1 | ||||||
Channel separation | DC | ±0.1 | µV/V | ||||
INPUT BIAS OPERATION | |||||||
IB | Input bias current | VCM = 0 V | TA = 25°C | ±0.3 | ±2 | nA | |
TA = –40°C to 85°C | ±4 | ||||||
TA = –40°C to 125°C | ±7 | ||||||
IOS | Input offset current | VCM = 0 V | TA = 25°C | ±0.1 | ±2 | nA | |
TA = –40°C to 85°C | ±4 | ||||||
TA = –40°C to 125°C | ±7 | ||||||
NOISE | |||||||
en p-p | Input voltage noise | f = 0.1 Hz to 10 Hz | 0.09 | µVPP | |||
en | Noise density | f = 10 Hz | 2.5 | nV/√Hz | |||
f = 100 Hz | 2.25 | ||||||
f = 1 kHz | 2.2 | ||||||
In | Input current noise density | f = 1 kHz | 400 | fA/√Hz | |||
INPUT VOLTAGE RANGE | |||||||
VCM | Common-mode voltage range | (V–) + 1.5 | (V+) – 1.5 | V | |||
CMRR | Common-mode rejection ratio | (V–) + 1.5 V < VCM < (V+) – 1.5 V | 132 | 140 | dB | ||
(V–) + 1.5 V < VCM < (V+) – 1.5 V, TA = –40°C to 125°C |
120 | 130 | |||||
INPUT IMPEDANCE | |||||||
Differential | 400 || 9 | kΩ || pF | |||||
Common-mode | 109 || 0.5 | Ω || pF | |||||
OPEN-LOOP GAIN | |||||||
AOL | Open-loop voltage gain | (V–) + 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ | TA = 25°C | 126 | 132 | dB | |
TA = –40°C to 125°C | 120 | ||||||
(V–) + 0.6 V < VO < (V+) – 0.6 V, RL = 600 Ω(1) | TA = 25°C | 114 | 120 | ||||
TA = –40°C to 85°C | 110 | ||||||
FREQUENCY RESPONSE | |||||||
GBW | Gain bandwidth product | 18 | MHz | ||||
SR | Slew rate | 6.4 | V/µs | ||||
Phase margin (Φm) | RL = 10 kΩ, CL = 25 pF | 80 | degrees | ||||
tS | Settling time | 0.1%, G = –1, 10-V step, CL = 100 pF | 2.1 | µs | |||
0.0015% (16-bit), G = –1, 10-V step, CL = 100 pF | 2.6 | ||||||
Overload recovery time | G = –10 | 0.5 | µs | ||||
Total harmonic distortion + noise (THD+N) | G = +1, f = 1 kHz, VO = 20 VPP, 600 Ω | 0.000025 | % | ||||
OUTPUT | |||||||
Voltage output swing | RL = 10 kΩ, AOL > 130 dB | (V–) + 0.2 | (V+) – 0.2 | V | |||
RL = 600 Ω, AOL > 114 dB | (V–) + 0.6 | (V+) – 0.6 | |||||
RL = 10 kΩ, AOL > 120 dB, TA = –40°C to 125°C | (V–) + 0.2 | (V+) – 0.2 | |||||
ISC | Short-circuit current | VS = ±18 V | ±65 | mA | |||
CLOAD | Capacitive load drive (stable operation) |
See Section 6.7 | |||||
ZO | Open-loop output impedance | See Section 6.7 | |||||
POWER SUPPLY | |||||||
IQ | Quiescent current (per amplifier) |
IO = 0 A | TA = 25°C | 2.2 | 2.5 | mA | |
TA = –40°C to 125°C | 3.25 |
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
f = 1 kHz | RL = 600 Ω |
5 typical units |
G = –10 |
G = +1 | 10-mV step, CL = 100 pF, RL = 600 Ω |
G = +1 | 10-V step, CL = 100 pF, RL = 600 Ω |
PRF = –10 dBm |
VOUT = 3.5 VRMS | RL = 600 Ω | |
5 typical units |
5 typical units |
G = –10 |
G = –1 | 10-mV step, CL = 100 pF, RL = 600 Ω |
G = –1 | 10-V step, CL = 100 pF, RL = 600 Ω |
10-V step |
The OPAx210 are the next generation of the OPAx209 operational amplifiers. The OPAx210 offer improved input offset voltage, offset voltage temperature drift, input bias current, and lower 1/f noise corner frequency. In addition, these devices offer excellent overall performance with high CMRR, PSRR, and AOL.The OPAx210 precision operational amplifiers are unity-gain stable, and free from unexpected output and phase reversal. Applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. Section 7.2 shows a simplified schematic of the OPAx210. The die uses a SiGe bipolar process and contains 180 transistors.
The OPAx210 op amps can be used with single or dual supplies within an operating range of VS = 4.5 V (±2.25 V) up to 36 V (±18 V).
In addition, key parameters are specified over the temperature range of TA = –40°C to +125°C. Parameters that vary significantly with operating voltage or temperature are shown in Section 6.7.
The input pins of the OPAx210 are protected from excessive differential voltage with back-to-back diodes, as shown in Figure 7-1. In most circuit applications, the input protection circuitry has no consequence. However, in low-gain or G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly enough to the input ramp. This effect is illustrated in Figure 6-35 and Figure 6-36 in Section 6.7. If the input signal is fast enough to create this forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can be used to limit the signal input current. This input series resistor degrades the low-noise performance of the OPAx210. See Section 7.3.3 for further information on noise performance.
Figure 7-1 shows an example configuration that implements a current-limiting feedback resistor.
Figure 7-2 shows the total circuit noise for varying source impedances with the op amp in a unity-gain configuration (no feedback resistor network, and therefore, no additional noise contributions). Two different op amps are shown with the total circuit noise calculated. The OPAx210 have very low voltage noise, making these devices a great choice for low source impedances (less than 2 kΩ). As a comparable, precision FET-input op amp (very low current noise), the OPA827 has somewhat higher voltage noise, but lower current noise. The device provides excellent noise performance at moderate to high source impedance (10 kΩ and up). For source impedance lower than 300 Ω, the OPA211 may provide lower noise.
The equation in Figure 7-2 shows the calculation of the total circuit noise, with these parameters:
For more details on calculating noise, see Section 8.1.1.
The OPAx210 have internal phase-reversal protection. Many FET- and bipolar-input op amps exhibit a phase reversal when the input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input circuitry of the OPAx210 prevents phase reversal with excessive common-mode voltage; instead, the output limits into the appropriate rail (see Figure 6-30).
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly.
It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event. See Figure 7-3 for an illustration of the ESD circuits contained in the OPAx210 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where they meet at an absorption device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or more of the steering diodes. Depending on the path that the current takes, the absorption device may activate. The absorption device has a trigger, or threshold voltage, that is greater than the normal operating voltage of the OPAx210 but less than the device breakdown voltage level. After this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit such as the one Figure 7-3 shows, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption device.
Figure 7-3 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage, +VS, by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while power supplies +VS, –VS, or both are at 0 V.
Again, the answer depends on the supply characteristic while at 0 V, or at a level less than the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier supply current may be supplied by the input source through the current steering diodes. This state is not a normal bias condition; the amplifier will not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistance in the input path.
If there is an uncertainty about the ability of the supply to absorb this current, external transient voltage suppressor (TVS) diodes may be added to the supply pins as shown in Figure 7-3. The breakdown voltage must be selected so that the diode does not turn on during normal operation. However, the breakdown voltage must be low enough so that the TVS diode conducts if the supply pin begins to rise to greater than the safe operating supply voltage level.
The OPAx210 are operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum power-supply voltage for the OPAx210 is 36 V (±18 V).
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
The OPAx210 are unity-gain stable, precision operational amplifiers with very low noise. Applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the resistance. This function is plotted in Figure 7-2. The source impedance is usually fixed; consequently, select the op amp and the feedback resistors to minimize the respective contributions to the total noise.
Figure 8-1 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the op amp reacts with the feedback resistors to create additional noise components. However, the extremely low current noise of the OPAx210 means that the device current noise contribution can be neglected.
Generally, the feedback resistor values are chosen to make these noise sources negligible. Low impedance feedback resistors load the output of the amplifier. The equations for total noise are shown for both configurations.
Low-pass filters are commonly used in signal processing applications to reduce noise and prevent aliasing. The OPAx210 are designed to construct high-speed, high-precision active filters. Figure 8-2 shows a second-order, low-pass filter commonly encountered in signal-processing applications.
Use the following parameters for this design example:
The infinite-gain, multiple-feedback circuit for a low-pass network function is shown in Figure 8-2. Use Equation 1 to calculate the voltage transfer function.
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are calculated by Equation 2:
During an ultrasound send-receive cycle, the magnitude of reflected signal depends on the depth of penetration. The ultrasound signal incident on the receiver decreases in amplitude as a function of the time elapsed since transmission. The time gain control (TGC) system helps achieve the best possible signal-to-noise ratio (SNR), even with the decreasing signal amplitude. When the image is displayed, similar materials have similar brightness, regardless of depth. Linear-in-dB gain, which means the decibel gain is a linear function of the control voltage (VCNTL), is used to generate this image.
There are multiple approaches for a TGC control circuit that are based on the type of DAC. Figure 8-4 shows a high-level block diagram for the topology using a current-output multiplying DAC (MDAC) to generate the drive for VCNTL. The op amp used for current-to-voltage (I-to-V) conversion must have low-voltage noise, as well as low-current noise density. The current density helps reduce the overall noise performance because of the DAC output configuration. The DAC output can go up to ±10 V; therefore, the op amp must have bipolar operation. The OPAx210 is used here because of the low-voltage noise density of 2.2 nV/√Hz, low-current noise density of 500 fA/√Hz, rail-to-rail output, and the ability to accept a wide supply range of ±2.25 V to ±18 V and provide rail-to-rail output. The low offset voltage and offset drift of the OPAx210 facilitate excellent dc accuracy for the circuit.
The OPAx210 is used to filter and buffer the 10-V reference voltage generated by the REF5010. The REF5010 serves as the reference voltage for the DAC8802, which generates a current output on IOUT corresponding to the digital input code. The IOUT pin of the DAC8802 is connected to the virtual ground (negative terminal) of the OPAx210; the feedback resistor (RFB is internal to the DAC8802) is connected to the output of the OPAx210, and results in a current-to-voltage conversion. The output of the OPAx210 has a range of –10 V to 0 V, which is fed to the THS4130 configured as a Sallen-Key filter. Finally, the 10-V range is attenuated down to a 1.5-V range, with a common-mode voltage of 0.75 V using a resistive attenuator. See the 2.3-nV/√Hz, Differential, Time Gain Control DAC Reference Design for Ultrasound for an in-depth analysis of Figure 8-4.
The OPAx210 are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in Section 6.7.
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including the following guidelines: