SBOS761 November   2015 OPA2211-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = ±2.25 to ±18 V
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Protection
      2. 7.3.2 Noise Performance
      3. 7.3.3 Basic Noise Calculations
      4. 7.3.4 Total Harmonic Distortion Measurements
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Overstress
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Total Harmonic Distortion Measurements
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Operating Voltage
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage VS = (V+) – (V–) 40 V
Input voltage (V–) – 0.5 (V+) + 0.5 V
Input current (any pin except power-supply pins) –10 10 mA
Output short-circuit(2) Continuous
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage (V+ – V–) 4.5 (±2.25) 36 (±18) V
Operating temperature, TJ –55 125 °C

6.4 Thermal Information

THERMAL METRIC(1) OPA2211-EP UNIT
DRG (WSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 47.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51.8 °C/W
RθJB Junction-to-board thermal resistance 21.8 °C/W
ψJT Junction-to-top characterization parameter 0.7 °C/W
ψJB Junction-to-board characterization parameter 21.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: VS = ±2.25 to ±18 V

at TJ = 25°C, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Input offset voltage VOS VS = ±15 V ±50 ±175 μV
Over temperature TJ = –55°C to 125°C ±350 µV
Drift dVOS/dT TJ = –55°C to 125°C 0.35 μV/°C
vs power supply PSRR VS = ±2.25 V to ±18 V 0.1 1 μV/V
Over temperature 3 μV/V
INPUT BIAS CURRENT
Input bias current IB VCM = 0 V, TJ = –55°C to 125°C ±50 ±350 nA
Offset current IOS VCM = 0 V, TJ = –55°C to 125°C ±20 ±200 nA
NOISE
Input voltage noise en ƒ = 0.1 Hz to 10 Hz 80 nVPP
Input voltage noise density ƒ = 10 Hz 2 nV/√Hz
ƒ = 100 Hz 1.4 nV/√Hz
ƒ = 1 kHz 1.1 nV/√Hz
Input current noise density In ƒ = 10 Hz 3.2 pA/√Hz
ƒ = 1 kHz 1.7 pA/√Hz
INPUT VOLTAGE RANGE
Common-mode voltage range VCM VS ≥ ±5 V (V–) + 1.8 (V+) – 1.4 V
VS < ±5 V (V–) + 2 (V+) – 1.4 V
Common-mode rejection ratio CMRR VS ≥ ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V, TJ = –55°C to 125°C 114 120 dB
VS < ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V, TJ = –55°C to 125°C 106 120 dB
INPUT IMPEDANCE
Differential 20k || 8 Ω || pF
Common-mode 109 || 2 Ω || pF
OPEN-LOOP GAIN
Open-loop voltage gain AOL (V–) + 0.2 V ≤ VO ≤ (V+) – 0.2V,
RL = 10 kΩ, TJ = –55°C to 125°C		 114 130 dB
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V,
RL = 600 Ω		 110 114 dB
Over temperature AOL (V–) + 0.6 V ≤ VO ≤ (V+) – 0.6V,
IO ≤ 15 mA, TJ = –55°C to 125°C		 100 dB
FREQUENCY RESPONSE
Gain-bandwidth product GBW G = 100 80 MHz
G = 1 45 MHz
Slew rate SR 27 V/μs
Settling time, 0.01% tS VS = ±15 V, G = –1, 10-V step, CL = 100 pF 400 ns
0.0015% (16-bit) VS = ±15 V, G = –1, 10-V step, CL = 100 pF 700 ns
Overload recovery time G = –10 500 ns
Total harmonic distortion + noise THD+N G = +1, ƒ = 1kHz,
VO = 3VRMS, RL = 600 Ω		 0.000015%
–136 dB
OUTPUT
Voltage output VOUT RL = 10 kΩ, AOL ≥ 114 dB, TJ = –55°C to 125°C (V–) + 0.2 (V+) – 0.2 V
RL = 600 Ω, AOL ≥ 110 dB (V–) + 0.6 (V+) – 0.6 V
IO < 15 mA, AOL ≥ 100 dB, TJ = –55°C to 125°C (V–) + 0.6 (V+) – 0.6 V
Short-circuit current ISC +30/–45 mA
Capacitive load drive CLOAD See Typical Characteristics pF
Open-loop output impedance ZO ƒ = 1MHz 5 Ω
POWER SUPPLY
Specified voltage VS ±2.25 ±18 V
Quiescent current (per channel) IQ IOUT = 0 A 3.6 4.5 mA
Over temperature TJ = –55°C to 125°C 6 mA
TEMPERATURE RANGE
Operating range TJ –55 125 °C

6.6 Typical Characteristics

At TJ = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
OPA2211-EP tc_v_dens-frq_bos377.gif
Figure 1. Input Voltage Noise Density vs Frequency
OPA2211-EP fig6_tc_channel-sep-frq_bos638.gif
Figure 3. Channel Separation vs Frequency
OPA2211-EP tc_psrr-frq_bos377.gif
Figure 5. Power-Supply Rejection Ratio vs Frequency (Referred to Input)
OPA2211-EP tc_oloop-frq_bos377.gif
Figure 7. Open-Loop Output Impedance vs Frequency
OPA2211-EP tc_oloop-tmp_bos377.gif
Figure 9. Normalized Open-Loop Gain vs Temperature
OPA2211-EP tc_histo_drift_bos377.gif
Figure 11. Offset Voltage Drift Production Distribution
OPA2211-EP tc_vo_vcm_bos377.gif
Figure 13. Offset Voltage vs Common-Mode Voltage
OPA2211-EP tc_ios-vs_bos377.gif
Figure 15. Input Offset Current vs Supply Voltage
OPA2211-EP tc_ib-vs_bos377.gif
Figure 17. Input Bias Current vs Supply Voltage
OPA2211-EP tc_iq-tmp_bos377.gif
Figure 19. Quiescent Current vs Temperature
OPA2211-EP tc_norm_iq-t_bos377.gif
Figure 21. Normalized Quiescent Current vs Time
OPA2211-EP tc_sm_step_10pf_n1_bos638.gif
Figure 23. Small-Signal Step Response (100 mV)
OPA2211-EP tc_sm_step_10pf_p1_bos377.gif
Figure 25. Small-Signal Step Response (100 mV)
OPA2211-EP tc_oshoot-cload_bos377.gif
Figure 27. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
OPA2211-EP tc_lg_step_p1_bos377.gif
Figure 29. Large-Signal Step Response
OPA2211-EP tc_lg_pos_10_bos377.gif
Figure 31. Large-Signal Positive Settling Time (10 VPP, CL = 10 pF)
OPA2211-EP tc_lg_neg_10_bos377.gif
Figure 33. Large-Signal Negative Settling Time (10 VPP, CL = 10 pF)
OPA2211-EP tc_pos_recov_bos377.gif
Figure 35. Positive Overload Recovery
OPA2211-EP tc_no_phase_bos377.gif
Figure 37. No Phase Reversal
OPA2211-EP tc_cur_dens-frq_bos377.gif
Figure 2. Input Current Noise Density vs Frequency
OPA2211-EP tc_noise_bos377.gif
Figure 4. 0.1-Hz to 10-Hz Noise
OPA2211-EP tc_cmrr-frq_bos377.gif
Figure 6. Common-Mode Rejection Ratio vs Frequency
OPA2211-EP tc_g_phase-frq_bos377.gif
Figure 8. Gain and Phase vs Frequency
OPA2211-EP tc_histo_bos377.gif
Figure 10. Offset Voltage Production Distribution
OPA2211-EP tc_ib_ios-tmp_bos377.gif
Figure 12. IB and IOS Current vs Temperature
OPA2211-EP tc_vos_warmup_bos377.gif
Figure 14. VOS Warmup
OPA2211-EP tc_ios-vcm_bos377.gif
Figure 16. Input Offset Current vs Common-Mode Voltage
OPA2211-EP tc_ib-vcm_bos377.gif
Figure 18. Input Bias Current vs Common-Mode Voltage
OPA2211-EP tc_iq-vs_bos377.gif
Figure 20. Quiescent Current vs Supply Voltage
OPA2211-EP tc_cur-tmp_bos377.gif
Figure 22. Short-Circuit Current vs Temperature
OPA2211-EP tc_sm_step_100pf_n1_bos638.gif
Figure 24. Small-Signal Step Response (100 mV)
OPA2211-EP tc_sm_step_100pf_p1_bos377.gif
Figure 26. Small-Signal Step Response (100 mV)
OPA2211-EP tc_lg_step_n1_bos377.gif
Figure 28. Large-Signal Step Response
OPA2211-EP tc_lg_pos_100_bos377.gif
Figure 30. Large-Signal Positive Settling Time
(10 VPP, CL = 100 pF)
OPA2211-EP tc_lg_neg_100_bos377.gif
Figure 32. Large-Signal Negative Settling Time (10 VPP, CL = 100 pF)
OPA2211-EP tc_neg_recov_bos377.gif
Figure 34. Negative Overload Recovery
OPA2211-EP tc_vo-io_claw_bos377.gif
Figure 36. Output Voltage vs Output Current