SBOSAA1H April   2022  – November 2024 OPA2310 , OPA310 , OPA4310

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operating Voltage
      2. 7.3.2  Rail-to-Rail Input
      3. 7.3.3  Rail-to-Rail Output
      4. 7.3.4  Capacitive Load and Stability
      5. 7.3.5  Overload Recovery
      6. 7.3.6  EMI Rejection
      7. 7.3.7  ESD and Electrical Overstress
      8. 7.3.8  Input ESD Protection
      9. 7.3.9  Shutdown Function
      10. 7.3.10 Packages with an Exposed Thermal Pad
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 OPAx310 Low-Side, Current Sensing Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4.     Trademarks
    5. 9.4 Electrostatic Discharge Caution
    6. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics

For VS = (V+) – (V–) = 1.5 V to 5.5 V (±0.75 V to ±2.75 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– ±0.25 ±1.3 mV
VCM = V– TA = –40°C to 125°C ±1.4
dVOS/dT Input offset voltage drift VCM = V– TA = –40°C to 125°C ±0.5 µV/℃
PSRR Input offset voltage versus power supply VS = 1.5 V to 5.5 V , VCM = V– ±10 ±50 µV/V
Channel separation f = 10 kHz ±1 µV/V
INPUT BIAS CURRENT
IB Input bias current (1) VS = 1.8 V and VS = 5 V ±1 ±30 pA
IOS Input offset current (1) VS = 1.8 V and VS = 5 V ±0.5 ±25 pA
NOISE
EN Input voltage noise f  = 0.1 to 10 Hz   4 μVPP
eN Input voltage noise density f = 100 Hz 32 nV/√Hz
f = 1 kHz   16  
f = 10 kHz   13  
iN Input current noise (3) f = 1 kHz   10   fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (1) VS = 1.8 V TA = –40°C to 125°C (V–) (V+) V
Common-mode voltage range (1) VS = 5.5 V TA = –40°C to 125°C (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode
rejection ratio		 VS = 1.8 V, (V–) ≤ VCM ≤ (V+) – 0.6 V 75 85 dB
VS = 1.8 V, (V–) ≤ VCM ≤ (V+) – 0.6 V TA = –40°C to 125°C 65 78 dB
VS = 5.5 V, (V–) ≤ VCM ≤ (V+) – 0.6 V 83 95 dB
VS = 5.5 V, (V–) ≤ VCM ≤ (V+) – 0.6 V TA = –40°C to 125°C 75 85 dB
Full Range: VS = 1.8 V, (V–) ≤ VCM ≤ (V+) TA = –40°C to 125°C 57.5 70
Full Range: VS = 5.5 V
(V–) – 0.1 V  ≤ VCM ≤ (V+) + 0.1 V		 TA = –40°C to 125°C 66.5 80
INPUT IMPEDANCE
ZID Differential
Input
Impedance		 80 || 1.4 GΩ || pF
ZICM Common-mode
Input
Impedance		 100 || 0.5 GΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 1.8 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ to VS / 2		 102 115 dB
Open-loop voltage gain(2) VS = 1.8 V, (V–) + 0.10 V < VO < (V+) – 0.10 V,
RL = 2 kΩ to VS / 2		 95 105 dB
VS = 5.5 V, (V–) + 0.10 V < VO < (V+) – 0.10 V,
RL = 10 kΩ to VS / 2		 109 125 dB
Open-loop voltage gain VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ to VS / 2		 105 115 dB
VS = 1.8 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ to VS / 2		 TA = –40°C to 125°C 90 100 dB
VS = 1.8 V, (V–) + 0.10 V < VO < (V+) – 0.10 V,
RL = 2 kΩ to VS / 2		 90
VS = 5.5 V, (V–) + 0.10 V < VO < (V+) – 0.10 V,
RL = 10 kΩ to VS / 2		 105
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ to VS / 2		 90 100
Open-loop voltage gain (6) VS = 3.3 V, (V–) + 0.25 V < VO < (V+) – 0.25 V,
IL = ±50 mA 		 TA = 25°C 80 102 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product VS = 1.8 V, G = +1, RL = 10 kΩ, CL = 100 pF 2.5 MHz
VS = 5.5 V, G = +1, RL = 10 kΩ, CL = 100 pF 3 MHz
SR Slew rate VS = 1.8 V, G = +1, RL = 10 kΩ 2.8 V/μs
VS = 5.5 V, G = +1, RL = 10 kΩ 3 V/μs
THD+N Total harmonic distortion + noise (4) VS = 5.5 V, G = +1, VO = 1 VRMS, f = 1 kHz,
RL = 10 kΩ to VS / 2		 0.0005 %
VS = 5.5 V, G = +1, VO = 1 VRMS, f = 1 kHz,
RL = 2 kΩ to VS / 2		 0.0035 %
VS = 5.5 V, G = +1, VO = 1 VRMS, f = 1 kHz,
RL = 600 Ω to VS / 2		 0.0080 %
tS Settling time To 0.1%, VS = 5.5 V, VSTEP = 4 V, G = +1, CL = 10 pF 1.8 μs
To 0.1%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL = 10 pF 1.3
To 0.01%, VS = 5.5 V, VSTEP = 4 V, G = +1, CL = 10 pF 2.3
To 0.01%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL = 10 pF 1.6
PM Phase margin G = +1, RL = 10 kΩ connected to VS/2, CL = 10 pF 60 °
CL Drive Cap Load Drive G = +1, RL = 10 kΩ connected to VS/2, Phase Margin = 40° 75 pF
G = +1, RL = 10 kΩ connected to VS/2,
No Sustained Oscillations		 250 pF
toverload Overload recovery time VIN  × gain > VS 0.6 μs
EMIRR Electro-magnetic interference rejection ratio f = 1.8 GHz, VIN_EMIRR = 100 mV 75 dB
OUTPUT
VOH Voltage output swing from positive rail VS = 1.8 V, RL = 2 kΩ to VS / 2   10 21 mV
VS = 1.8 V, RL = 10 kΩ to VS / 2   2 11
VS = 1.8 V, RL = 2 kΩ to VS / 2 TA = –40°C to 125°C   51
VS = 1.8 V, RL = 10 kΩ to VS / 2 TA = –40°C to 125°C   26
VS = 5.5 V, RL = 2 kΩ to VS / 2   3.5 20
VS = 5.5 V, RL = 10 kΩ to VS / 2   0.75 9
VS = 5.5 V, RL = 2 kΩ to VS / 2 TA = –40°C to 125°C   30
VS = 5.5 V, RL = 10 kΩ to VS / 2 TA = –40°C to 125°C   14
VOL Voltage output swing from negative rail VS = 1.8 V, RL = 2 kΩ to VS / 2   5.5 15
VS = 1.8 V, RL = 10 kΩ to VS / 2   1.2 10
VS = 1.8 V, RL = 2 kΩ to VS / 2 TA = –40°C to 125°C   45
VS = 1.8 V, RL = 10 kΩ to VS / 2 TA = –40°C to 125°C   25
VS = 5.5 V, RL = 2 kΩ to VS / 2   3.5 17.5
VS = 5.5 V, RL = 10 kΩ to VS / 2   0.75 10
VS = 5.5 V, RL = 2 kΩ to VS / 2 TA = –40°C to 125°C   27.5
VS = 5.5 V, RL = 10 kΩ to VS / 2 TA = –40°C to 125°C   11
ISC Short-circuit current (5) VS = 1.8 V ±20 mA
Short-circuit current (2) (5) VS = 1.8 V, TA = –40℃ to 125℃ ±6 mA
Short-circuit current (5) VS = 5.5 V, OPA2310  ±75 ±150 mA
ISC Short-circuit current (5) VS = 5.5 V, OPA310 and OPA4310 ±110 mA
ZO Open-loop output impedance f = 10 kHz 1000 Ω
POWER SUPPLY
IQ Quiescent current per amplifier VS = 1.5 V, IO = 0 A, SHDN = V+ for shutdown devices 165 190 µA
VS = 1.5 V, IO = 0 A, SHDN = V+ for shutdown devices TA = –40°C to 125°C 165 210 µA
VS = 5.5 V, IO = 0 A, SHDN = V+ for shutdown devices 165 200 µA
TA = –40°C to 125°C 215
Power-on time At TA = 25°C, VS = 5.5 V, VS ramp rate > 0.3 V/µs
 		 125 μs
SHUTDOWN
IQ_SHDN  Shutdown current per amplifier  All amplifiers disabled, SHDN = V–, OPA4310S 0.100 0.150 µA
All amplifiers disabled, SHDN = V–, OPA310S 0.265 0.475 µA
IQ_SHDN  Shutdown current per amplifier  All amplifiers disabled, SHDN = V–, OPA2310S 0.200 0.375 µA
IQ_SHDN  Shutdown current per amplifier (1) All amplifiers disabled, SHDN = V–, TA = –40℃ to 85℃, OPA4310S 0.300 µA
All amplifiers disabled, SHDN = V–, TA = –40℃ to 85℃, OPA310S 0.700 µA
IQ_SHDN  Shutdown current per amplifier (1) All amplifiers disabled, SHDN = V–, TA = –40℃ to 85℃, OPA2310S 0.600 µA
ZOUT_SHDN  Output impedance during shutdown  Amplifier disabled 43 || 11.5 GΩ || pF
VSHDN_IH  Logic high voltage (amplifier enabled)  (V–) + 1.2 V
VSHDN_IL Logic low voltage (amplifier disabled)  (V–) + 0.2 V
tON Amplifier enable time (full shutdown) (7) (1) G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V– 1 1.6 µs
tOFF Amplifier disable time (7)  G = +1, VCM = VS / 2, VO = 0.1 × VS / 2, RL connected to V– 1 µs
IB_SHDN SHDN pin input bias current (per pin)  (V+) ≥ SHDN ≥ (V–) + 1 V 50 nA
(V–) ≤ SHDN ≤ (V–) + 0.2 V 100
(1) Max data is specified based on characterization results. 
(2) Min data is specified based on characterization results. 
(3) Typical input current noise data is specified based on design simulation results.
(4) Third-order filter; bandwidth = 80 kHz at –3 dB.
(5) Short circuit current specified here is the average of sourcing and sinking short circuit currents.
(6) AOL is measured as the difference between (VOSA – VOSB) / (VOUTA – VOUTB). VOSA is the offset measured when the OUT pin is biased at (V+) - 0.25 V while the device sources 50 mA and VOSB is the offset measured when the OUT pin is biased at (V–) + 0.25 V while the device sinks 50 mA.
(7) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.