SBOS823
December 2018
OPA2313-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
EMIRR IN+ vs Frequency
4
Revision History
5
Pin Configuration and Functions
Pin Functions: OPA2313-Q1
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics: 5.5 V
6.6
Electrical Characteristics: 1.8 V
6.7
Typical Characteristics: Tables of Graphs
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Operating Voltage
7.3.2
Rail-to-Rail Input
7.3.3
Rail-to-Rail Output
7.3.4
Common-Mode Rejection Ratio (CMRR)
7.3.5
Capacitive Load and Stability
7.3.6
EMI Susceptibility and Input Filtering
7.3.7
Input and ESD Protection
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
System Examples
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
D|8
MSOI002K
DGK|8
MPDS028E
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sbos823_oa
sbos823_pm
6.8
Typical Characteristics
At T
A
= 25°C, V
S
= 5 V, R
L
= 10 kΩ connected to V
S
/ 2, and V
CM
= V
OUT
= V
S
/ 2, unless otherwise noted.
Figure 1.
Open-Loop Gain and Phase vs Frequency
Figure 3.
Quiescent Current vs Supply
Figure 5.
Offset Voltage Production Distribution
Figure 7.
Offset Voltage vs Common-Mode Voltage
Figure 9.
CMRR and PSRR vs Frequency
(Referred-to-Input)
Figure 11.
0.1-Hz to 10-Hz Input Voltage Noise
Figure 13.
Voltage Noise vs Common-Mode Voltage
Figure 15.
Open-Loop Output Impedance vs Frequency
Figure 17.
Output Voltage Swing vs Output Current (Over Temperature)
Figure 19.
Closed-Loop Gain vs Frequency
(Maximum Supply)
Figure 21.
Phase Margin vs Capacitive Load
Figure 23.
Small-Signal Pulse Response
(Maximum Supply)
Figure 25.
Large-Signal Pulse Response
(Maximum Supply)
Figure 27.
Negative Overload Recovery
Figure 29.
Channel Separation vs Frequency
Figure 31.
THD+N vs Output Amplitude
(Maximum Supply)
Figure 33.
EMIRR IN+ vs Frequency
Figure 2.
Open-Loop Gain vs Temperature
Figure 4.
Quiescent Current vs Temperature
Figure 6.
Offset Voltage Drift Distribution
Figure 8.
Offset Voltage vs Temperature
Figure 10.
CMRR and PSRR vs Temperature
Figure 12.
Input Voltage Noise Spectral Density vs Frequency
Figure 14.
Input Bias and Offset Current vs Temperature
Figure 16.
Maximum Output Voltage vs Frequency and Supply Voltage
Figure 18.
Closed-Loop Gain vs Frequency (Minimum Supply)
Figure 20.
Small-Signal Overshoot vs
Load Capacitance
Figure 22.
Small-Signal Pulse Response
(Minimum Supply)
Figure 24.
Large-Signal Pulse Response
(Minimum Supply)
Figure 26.
Positive Overload Recovery
Figure 28.
No Phase Reversal
Figure 30.
THD+N vs Output Amplitude
(Minimum Supply)
Figure 32.
THD+N vs Frequency