The OPA320 (single) and OPA2320 (dual) are a new generation of precision, low-voltage CMOS operational amplifiers optimized for very low noise and wide bandwidth while operating on a low quiescent current of only 1.45 mA.
The OPA320 series is ideal for low-power, single-supply applications. Low-noise (7 nV/√Hz) and high-speed operation also make them well-suited for driving sampling analog-to-digital converters (ADCs). Other applications include signal conditioning and sensor amplification.
The OPA320 features a linear input stage with zero-crossover distortion that delivers excellent common-mode rejection ratio (CMRR) of typically 114 dB over the full input range. The input common mode range extends 100 mV beyond the negative and positive supply rails. The output voltage typically swings within 10 mV of the rails.
In addition, the OPAx320 has a wide supply voltage range from 1.8 V to 5.5 V with excellent PSRR
(106 dB) over the entire supply range, making them suitable for precision, low-power applications that run directly from batteries without regulation.
The OPA320 (single version) is available in a 5-pin SOT23 package; the OPA320S shutdown single version is available in an 6-pin SOT23 package. The dual OPA2320 is offered in 8-pin SOIC, VSSOP, and SON packages, and the OPA2320S (dual with shutdown) in a 10-pin VSSOP package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
OPA320 | SOT-23 (5) | 2.90 mm × 1.60 mm |
OPA320S | SOT-23 (6) | 2.90 mm × 1.60 mm |
OPA2320 | VSSOP (8) | 3.00 mm × 3.00 mm |
SOIC (8) | 4.90 mm × 3.91 mm | |
SON (10) | 3.00 mm × 3.00 mm | |
OPA2320S | VSSOP (10) | 3.00 mm × 3.00 mm |
Changes from E Revision (June 2013) to F Revision
Changes from D Revision (November 2011) to E Revision
Changes from C Revision (August 2011) to D Revision
Changes from B Revision (March 2010) to C Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | OPA320 | OPA320S | ||
–IN | 4 | 4 | I | Negative (inverting) input |
+IN | 3 | 3 | I | Positive (noninverting) input |
OUT, VOUT | 1 | 1 | O | Output |
SHDN | — | 5 | I | Shutdown, active low |
V– | 2 | 2 | — | Negative (lowest) power supply |
V+ | 5 | 6 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOIC, VSSOP |
SON | ||
–IN A | 2 | 2 | I | Inverting input, channel A |
+IN A | 3 | 3 | I | Noninverting input, channel A |
–IN B | 6 | 6 | I | Inverting input, channel B |
+IN B | 5 | 5 | I | Noninverting input, channel B |
OUT A, VOUT A | 1 | 1 | O | Output, channel A |
OUT B, VOUT B | 7 | 7 | O | Output, channel B |
SHDN A | — | — | I | Shutdown, active low, channel A |
SHDN B | — | — | I | Shutdown, active low, channel B |
V– | 4 | 4 | — | Negative (lowest) power supply |
V+ | 8 | 8 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
–IN A | 2 | I | Inverting input, channel A |
+IN A | 3 | I | Noninverting input, channel A |
–IN B | 8 | I | Inverting input, channel B |
+IN B | 7 | I | Noninverting input, channel B |
OUT A, VOUT A | 1 | O | Output, channel A |
OUT B, VOUT B | 9 | O | Output, channel B |
SHDN A | 5 | I | Shutdown, active low, channel A |
SHDN B | 6 | I | Shutdown, active low, channel B |
V– | 4 | — | Negative (lowest) power supply |
V+ | 10 | — | Positive (highest) power supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | Supply, VS = (V+) – (V–) | 6 | V | |
Signal input pin(2) | (V–) – 0.5 | (V+) + 0.5 | ||
Current | Signal input pin(2) | –10 | 10 | mA |
Output short-circuit current(3) | Continuous | |||
Temperature | Operating range, TA | –40 | 150 | °C |
Junction, TJ | 150 | |||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
Machine model (MM) | ±200 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VS | Specified voltage | 1.8 | 5.5 | V |
TA | Specified temperature | –40 | 125 | °C |
THERMAL METRIC | OPA320 | OPA320S | UNIT | |
---|---|---|---|---|
DBV (SOT-23) | DBV (SOT-23) | |||
5 PINS | 6 PINS | |||
RθJA | Junction-to-ambient thermal resistance(1) | 219.3 | 177.5 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 107.5 | 108.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 57.5 | 27.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 7.4 | 13.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 56.9 | 26.9 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | — | — | °C/W |
THERMAL METRIC(1) | OPA2320 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | DGK (VSSOP) | DRG (SON) | |||
8 PINS | 8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 122.6 | 174.8 | 50.6 | °C/W |
RθJC(top) | Junction-to-case(top) thermal resistance | 67.1 | 43.9 | 54.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 64 | 95 | 25.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 13.2 | 2 | 0.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 63.4 | 93.5 | 25.3 | °C/W |
RθJC(bot) | Junction-to-case(bottom) thermal resistance | — | — | 5.7 | °C/W |
THERMAL METRIC(1) | OPA2320S | UNIT | |
---|---|---|---|
DGS (VSSOP) | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 171.5 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 43 | °C/W |
RθJB | Junction-to-board thermal resistance | 91.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 89.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | ||||||||
VOS | Input offset voltage | 40 | 150 | µV | ||||
dVOS/dT | Input offset voltage vs temperature |
VS = 5.5 V, TA = –40°C to 125°C | 1.5 | 5 | µV/°C | |||
PSR | Input offset voltage vs power supply |
VS = 1.8 V to 5.5 V, TA = 25°C | 5 | 20 | µV/V | |||
VS = 1.8 V to 5.5 V, TA = –40°C to 125°C | 15 | |||||||
Channel separation | 1 kHz | 130 | dB | |||||
INPUT VOLTAGE | ||||||||
VCM | Common-mode voltage | (V–) – 0.1 | (V+) + 0.1 | V | ||||
CMRR | Common-mode rejection ratio | VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V, TA = 25°C | 100 | 114 | dB | |||
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V, TA = –40°C to 125°C | 96 | |||||||
INPUT BIAS CURRENT | ||||||||
IB | Input bias current | TA = 25°C | ±0.2 | ±0.9 | pA | |||
TA = –40°C to 85°C | ±50 | |||||||
TA = –40°C to 125°C | OPA2320 and OPA2320S | ±400 | ||||||
OPA320 and OPA320S | ±600 | |||||||
IOS | Input offset current | TA = 25°C | ±0.2 | ±0.9 | pA | |||
TA = –40°C to 85°C | ±50 | |||||||
TA = –40°C to 125°C | ±400 | |||||||
NOISE | ||||||||
Input voltage noise | f = 0.1 Hz to 10 Hz | 2.8 | µVPP | |||||
en | Input voltage noise density | f = 1 kHz | 8.5 | nV/√Hz | ||||
f = 10 kHz | 7 | |||||||
in | Input current noise density | f = 1 kHz | 0.6 | fA/√Hz | ||||
INPUT CAPACITANCE | ||||||||
Differential | 5 | pF | ||||||
Common mode | 4 | pF | ||||||
OPEN-LOOP GAIN | ||||||||
AOL | Open-loop voltage gain | 0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ, TA = 25°C | 114 | 132 | dB | |||
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ, TA = –40°C to 125°C | 100 | 130 | ||||||
0.2 V < VO < (V+) – 0.2 V, RL = 2 kΩ, TA = 25°C | 108 | 123 | ||||||
0.2 V < VO < (V+) – 0.2 V, RL = 2 kΩ, TA = –40°C to 125°C | 96 | 130 | ||||||
PM | Phase margin | VS = 5 V, CL = 50 pF | 47 | ° | ||||
FREQUENCY RESPONSE, VS = 5 V, CL = 50 pF | ||||||||
GBP | Gain bandwidth product | Unity gain | 20 | MHz | ||||
SR | Slew rate | G = +1 | 10 | V/µs | ||||
tS | Settling time | to 0.1%, 2-V step, G = +1 | 0.25 | µs | ||||
to 0.01%, 2-V step, G = +1 | 0.32 | |||||||
to 0.0015%, 2-V step, G = +1(1) | 0.5 | |||||||
Overload recovery time | VIN × G > VS | 100 | ns | |||||
THD+N | Total harmonic distortion + noise(2) | VO = 4 VPP, G = 1, f = 10 kHz, RL = 10 kΩ | 0.0005% | |||||
VO = 2 VPP, G = 1, f = 10 kHz, RL = 600 Ω | 0.0011% | |||||||
OUTPUT | ||||||||
VO | Voltage output swing from both rails | RL = 10 kΩ, TA = 25°C | 10 | 20 | mV | |||
RL = 2 kΩ, TA = 25°C | 25 | 35 | ||||||
RL = 10 kΩ, TA = –40°C to 125°C | 30 | |||||||
RL = 2 kΩ, TA = –40°C to 125°C | 45 | |||||||
ISC | Short-circuit current | VS = 5.5 V | ±65 | mA | ||||
CL | Capacitive load drive | See Typical Characteristics | ||||||
RO | Open-loop output resistance | IO = 0 mA, f = 1 MHz | 90 | Ω | ||||
SHUTDOWN (3) | ||||||||
IQSD | Quiescent current per amplifier | All amplifiers disabled, SHDN = V– | 0.1 | 0.5 | µA | |||
OPA2320S only, SHDN A = VS–, SHDN B = VS+ | 1.6 | mA | ||||||
OPA2320S only, SHDN A = VS+, SHDN B = VS– | 1.6 | |||||||
VIH | High-level input voltage | Amplifier enabled, VS– + 0.7 [(VS+) + |VS–|] | 0.7 × VS+ | 5.5 | V | |||
VIL | Low-level input voltage | Amplifier disabled, VS– + 0.3 [(VS+) + |VS–|] | 0.3 × VS+ | V | ||||
tON | Amplifier enable time(4) | G = 1, VOUT = 0.1 × VS/2, full shutdown(5) | 20 | µs | ||||
OPA2320S only, partial shutdown(5) | 6 | |||||||
tOFF | Amplifier disable time(4) | G = 1, VOUT = 0.1 × VS/2 | 3 | µs | ||||
SHDN pin input bias current (per pin) | VIH = 5 V | 0.13 | µA | |||||
VIL = 0 V | 0.04 | |||||||
POWER SUPPLY | ||||||||
VS | Specified voltage | 1.8 | 5.5 | V | ||||
IQ | Quiescent current per amplifier, OPA320 and OPA320S |
IO = 0 mA, VS = 5.5 V, TA = 25°C | 1.5 | 1.75 | mA | |||
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C | 1.85 | |||||||
Quiescent current per amplifier, OPA2320 and OPA2320S |
IO = 0 mA, VS = 5.5 V, TA = 25°C | 1.45 | 1.6 | mA | ||||
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C | 1.7 | |||||||
Power-on time | V+ = 0 V to 5 V, to 90% IQ level | 28 | µs |
The OPA320 family of operational amplifiers (op amps) are high-speed, precision amplifiers, perfectly suited to drive 12-, 14-, and 16-bit analog-to-digital converters. Low output impedance with flat frequency characteristics and zero-crossover distortion circuitry enable high linearity over the full input common mode range, achieving true rail-to-rail input from a 1.8-V to 5.5-V single supply.
The OPA320 series op amps are unity-gain stable and can operate on a single-supply voltage (1.8 V to 5.5 V), or a split-supply voltage (±0.9 V to ±2.75 V), making them highly versatile and easy to use. The power-supply pins should have local bypass ceramic capacitors (typically 0.001 µF to 0.1 µF). The OPA320 amplifiers are fully specified from 1.8 V to 5.5 V and over the extended temperature range of –40°C to 125°C. Parameters that can exhibit variance with regard to operating voltage or temperature are presented in the Typical Characteristics.
The OPA320 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of input and output pins, this protection primarily consists of current-steering diodes connected between the input and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection, provided that the current is limited to 10 mA as stated in the Absolute Maximum Ratings. Many input signals are inherently current-limited to less than 10 mA; therefore, a limiting resistor is not required. Figure 33 shows how a series input resistor (RS) may be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the value should be kept to the minimum in noise-sensitive applications.
The OPA320 product family features true rail-to-rail input operation, with supply voltages as low as ±0.9 V (1.8 V). The design of the OPA320 amplifiers include an internal charge-pump that powers the amplifier input stage with an internal supply rail at approximately 1.6 V above the external supply (VS+). This internal supply rail allows the single differential input pair to operate and remain very linear over a very wide input common mode range. A unique zero-crossover input topology eliminates the input offset transition region typical of many rail-to-rail, complementary input stage operational amplifiers. This topology allows the OPA320 to provide superior common-mode performance (CMRR > 110 dB, typical) over the entire common-mode input range, which extends 100 mV beyond both power-supply rails. When driving analog-to-digital converters (ADCs), the highly linear VCM range of the OPA320 assures maximum linearity and lowest distortion.
The OPA320 op amps are designed to be immune to phase reversal when the input pins exceed the supply voltages, therefore providing further in-system stability and predictability. Figure 34 shows the input voltage exceeding the supply voltage without any phase reversal.
For optimum settling time and stability with high-impedance feedback networks, it may be necessary to add a feedback capacitor across the feedback resistor, RF, as shown in Figure 35. This capacitor compensates for the zero created by the feedback network impedance and the OPA320 input capacitance (and any parasitic layout capacitance). The effect becomes more significant with higher impedance networks.
NOINDENT:
Where CIN is equal to the OPA320 input capacitance (approximately 9 pF) plus any parasitic layout capacitance.For the circuit shown in Figure 35, the value of the variable feedback capacitor should be chosen so that the input resistance times the input capacitance of the OPA320 (typically 9 pF) plus the estimated parasitic layout capacitance equals the feedback capacitor times the feedback resistor calculated with Equation 1.
where
The capacitor value can be adjusted until optimum performance is obtained.
Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the operational amplifier, the dc offset observed at the amplifier output may shift from the nominal value while EMI is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While all operational amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The OPA320 operational amplifier family incorporates an internal input low-pass filter that reduces the amplifiers response to EMI. Both common mode and differential mode filtering are provided by the input filter. The filter is designed for a cutoff frequency of approximately 580 MHz (–3 dB), with a roll-off of 20 dB per decade.
The open-loop output impedance of the OPA320 common-source output stage is approximately 90 Ω. When the op amp is connected with feedback, this value is reduced significantly by the loop gain. For example, with 130 dB (typical) of open-loop gain, the output impedance is reduced in unity-gain to less than 0.03 Ω. For each decade rise in the closed-loop gain, the loop gain is reduced by the same amount, which results in a ten-fold increase in effective output impedance. While the OPA320 output impedance remains very flat over a wide frequency range, at higher frequencies the output impedance rises as the open-loop gain of the op amp drops. However, at these frequencies the output also becomes capacitive as a result of parasitic capacitance. This architecture in turn prevents the output impedance from becoming too high, which can cause stability problems when driving large capacitive loads. As mentioned previously, the OPA320 has excellent capacitive load drive capability for an op amp with its bandwidth.
The OPA320 is designed to be used in applications where driving a capacitive load is required. As with all op amps, there may be specific instances where the OPA320 can become unstable. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier is stable in operation. An op amp in the unity-gain (1-V/V) buffer configuration and driving a capacitive load exhibits a greater tendency to become unstable than an amplifier operated at a higher noise gain. The capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases. When operating in the unity-gain configuration, the OPA320 remains stable with a pure capacitive load up to approximately 1 nF.
The equivalent series resistance (ESR) of some very large capacitors (CL > 1 µF) is sufficient to alter the phase characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when observing the overshoot response of the amplifier at higher voltage gains, as shown in Figure 37. One technique for increasing the capacitive load drive capability of the amplifier operating in unity gain is to insert a small resistor (RS), typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 36.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. A possible problem with this technique is that a voltage divider is created with the added series resistor and any resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that reduces the output swing. The error contributed by the voltage divider may be insignificant. For instance, with a load resistance, RL = 10 kΩ and RS = 20 Ω, the gain error is only about 0.2%. However, when RL is decreased to 600 Ω, which the OPA320 is able to drive, the error increases to 7.5%.
Overload recovery time is the time it takes the output of the amplifier to come out of saturation and recover to the linear region. Overload recovery is particularly important in applications where small signals must be amplified in the presence of large transients. Figure 38 and Figure 39 show the positive and negative overload recovery times of the OPA320, respectively. In both cases, the time elapsed before the OPA320 comes out of saturation is less than 100 ns. In addition, the symmetry between the positive and negative recovery times allows excellent signal rectification without distortion of the output signal.
The SHDN (enable) pin function of the OPAx320S is referenced to the negative supply voltage of the operational amplifier. A logic level high enables the op amp. A valid logic high is defined as voltage [(V+) – 0.1 V], up to (V+), applied to the SHDN pin. A valid logic low is defined as [(V–) + 0.1 V], down to (V–), applied to the enable pin. The maximum allowed voltage applied to SHDN is 5.5 V with respect to the negative supply, independent of the positive supply voltage. This pin must either be connected to a valid high or a low voltage or driven, and not left as an open circuit.
The logic input is a high-impedance CMOS input. Dual op amp versions are independently controlled and quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be used to greatly reduce the average current and extend battery life. The enable time is 10 µs for full shutdown of all channels; disable time is 3 μs. When disabled, the output assumes a high-impedance state. This architecture allows the OPAx320S to be operated as a gated amplifier (or to have the device output multiplexed onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases with increased load resistance. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to mid-supply (VS / 2) is required. If using the OPAx320S without a load, the resulting turn-off time is significantly increased.
The OPA320 series uses the SON style package (also known as SON), which is a QFN with contacts on only two sides of the package bottom. This leadless package maximizes printed circuit board (PCB) space and offers enhanced thermal and electrical characteristics through an exposed pad. One of the primary advantages of the SON package is its low height (0.8 mm).
SON packages are physically small, have a smaller routing area, improved thermal performance, reduced electrical parasitics, and a pinout scheme that is consistent with other commonly-used packages (such as SOIC and VSSOP). Additionally, the absence of external leads eliminates bent-lead issues.
The SON package can easily be mounted using standard PCB assembly techniques. See Application Report, QFN/SON PCB Attachment (SLUA271) and Application Report, Quad Flatpack No-Lead Logic Packages (SCBA017), both available for download at www.ti.com.
NOTE
The exposed leadframe die pad on the bottom of the SON package should be connected to the most negative potential (V–).
The OPA320 family of operational amplifiers are operational when power-supply voltages between 1.8 V to 5.5 V are applied. Devices with an S suffix have a shutdown capability. For a detailed description of the shutdown function, see Shutdown Function.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The OPA320 family offers outstanding DC and AC performance. These devices operate up to a 5.5-V power supply and offer ultra-low input bias current and 20-MHz bandwidth. These features make the OPA320 family a robust operational amplifier for both battery-powered and industrial applications.
Wide gain bandwidth, low-input bias current, low input voltage, and current noise make the OPA320 an ideal wideband photodiode transimpedance amplifier. Low-voltage noise is important because photodiode capacitance causes the effective noise gain of the circuit to increase at high frequency.
The key elements to a transimpedance design, as shown in Figure 40, are the expected diode capacitance (CD), which should include the parasitic input common mode and differential-mode input capacitance (4 pF + 5 pF for the OPA320); the desired transimpedance gain (RF); and the gain-bandwidth (GBW) for the OPA320 (20 MHz). With these three variables set, the feedback capacitor value (CF) can be set to control the frequency response. CF includes the stray capacitance of RF, which is 0.2 pF for a typical surface-mount resistor.
To achieve a maximally-flat, second-order Butterworth frequency response, the feedback pole should be set as shown in Equation 2.
Bandwidth is calculated by Equation 3.
For even higher transimpedance bandwidth, consider the high-speed CMOS OPA380 (90-MHz GBW), OPA354 (100-MHz GBW), OPA300 (180-MHz GBW), OPA355 (200-MHz GBW), or OPA656/57 (400-MHz GBW).
For single-supply applications, the +IN input can be biased with a positive dc voltage to allow the output to reach true zero when the photodiode is not exposed to any light, and respond without the added delay that results from coming out of the negative rail; this configuration is shown in Figure 41. This bias voltage also appears across the photodiode, providing a reverse bias for faster operation.
For additional information, see the Application Bulletin Compensate Transimpedance Amplifiers Intuitively (SBOA055), available for download at www.ti.com.
To achieve the best performance, components should be selected according to the following guidelines:
For additional information, refer to the Application Bulletins Noise Analysis of FET Transimpedance Amplifiers (SBOA060), and Noise Analysis for High-Speed Op Amps (SBOA066), available for download at www.ti.com.
Many sensors have high source impedances that may range up to 10 MΩ, or even higher. The output signal of sensors often must be amplified or otherwise conditioned by means of an amplifier. The input bias current of this amplifier can load the sensor output and cause a voltage drop across the source resistance, as shown in Figure 42, where (VIN+ = VS – IBIAS × RS). The last term, IBIAS × RS, shows the voltage drop across RS. To prevent errors introduced to the system as a result of this voltage, an op amp with very low input bias current must be used with high impedance sensors. This low current keeps the error contribution by IBIAS × RS less than the input voltage noise of the amplifier, so that it does not become the dominant noise factor. The OPA320 series of op amps feature very low input bias current (typically 200 fA), and are therefore ideal choices for such applications.
The OPA320 series op amps are well-suited for driving sampling analog-to-digital converters (ADC's) with sampling speeds up to 1 MSPS. The zero-crossover distortion input stage topology allows the OPA320 to drive ADC's without degradation of differential linearity and THD.
The OPA320 can be used to buffer the ADC switched input capacitance and resulting charge injection while providing signal gain. Figure 44 shows the OPA320 configured to drive the ADS8326.
The OPA320 is well-suited for active filter applications that require a wide bandwidth, fast slew rate, low-noise, single-supply operational amplifier. Figure 45 shows a 500-kHz, second-order, low-pass filter using the multiple-feedback (MFB) topology. The components have been selected to provide a maximally-flat Butterworth response. Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is ideal for applications requiring predictable gain characteristics, such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted, relative to the input. If this inversion is not required, or not desired, a noninverting output can be achieved through one of these options:
MFB and Sallen-Key, low-pass and high-pass filter synthesis is quickly accomplished using TI’s FilterPro™ program. This software is available as a free download at www.ti.com.
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in. Use Equation 4 to calculate the voltage transfer function.
This circuit produces a signal inversion. For this circuit, the gain at DC and the lowpass cutoff frequency are calculated by Equation 5.
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH® Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH Design Center, WEBENCH Filter Designer allows you to design, optimize, and simulate complete multistage active filter solutions within minutes.